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the GP2021 is a 12 channel c/a code baseband correlator for use in navstar gps and glonass satellite navigation receivers. the GP2021 complements the gp2015 and gp2010 c/a code rf downconverters available from mitel semiconductor. the GP2021 is compatible with most 16 bit and 32 bit microprocessors, especially those from motorola and intel, with additional onCchip support for the arm60 32 bit risc processor. when the arm60 is used, the onCchip memory management functions allow implementation of a full gps receiver with minimal external logic. the GP2021 allows individual channel deCactivation, for systems not requiring full 12 channel operation, to save power and processor loading. receiver power may be further conserved by reducing the supply voltage to 2.2v under battery backup. although all system functions are disabled, the 32.768khz oscillator and real time clock are maintained for the microprocessor to estimate satellite visibility at power on to reduce signal acquisition time. a development system called the gps architect is available as a basis for receiver design using the GP2021 and associated products. features n 12 fully independent correlation channels n 1pps utc aligned timing output n onCchip dual uart and real time clock n compatible with most 16 and 32 bit microprocessors n memory control logic for arm60 microprocessor n low voltage, low current powerCdown mode n power dissipation 150mw typical n compatible with gp2015 and gp2010 rf front ends n battery backup voltage 2.2v (min) applications n gps navigation systems n high integrity combined gpsCglonass receivers n gps geodetic receivers n time transfer receivers ordering information GP2021/ig/gq1r fig.1 pin connections - top view gq80 GP2021 pin 1 pin 1 ident pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 description multi_fn_io power _good nreset_op narmsys xin xout txa txb rxa rxb nrom / nc neeprom / nc nspare_cs / nc v dd v ss nram / bc nw0 / nc nw1 / nc nw2 / nc nw3 / nc nrd / nc arm_ale / nc dbe / nc accum_int meas_int nbw / wrprog nmreq / discip2 nopc / nintelmot nrw / discip3 mclk / nc abort / micro_clk discio a22 / read vdd vss a21 / ncs a20 / wren a9 a8 a7 description a6 a5 a4 a3 a2 a1 / ale_ip a0 / nreset_ip d0 d1 d2 d3 d4 d5 d6 v dd v ss d7 d8 d9 d10 d11 d12 d13 d14 d15 pll_lock vdd discop v ss clk_t clk_i v ss sampclk v dd nbram / discip4 sign0 mag1 sign1 mag1 discip1 pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 ds4077 - 2.6 july 1996 GP2021 gps 12 channel correlator advance information related products part description datasheet reference gp2015 gps receiver rf front end ds4374 C tqfp 48 package gp2010 glps receiver rf front end ds4056 C pqfp 44 package dw9255 35.42mhz saw filter ds3861 p60arm 32 bit risc microprocessor ds3553 gps architect gps 12 channel ds4004 receiver development system
2 GP2021 table of contents heading page typical gps receiver 4 pin description 4 differences between real and complex_input mode 7 functional description 7 12 channel correlator 8 clock generator 8 timebase generator 8 status registers 9 sample latches 9 address decoder 9 bus interface 9 tracking modules 9 carrier dco 9 code dco 9 carrier cycle counter 9 c/a code generator 9 source selector 10 carrier mixers 10 code mixers 10 accumulate and dump 10 code phase counter 10 code slew counter 10 epoch counter 11 peripheral functions 11 dual uart 11 receiver 11 transmitter 11 reset 11 channel loopback 12 real time clock (rtc) and watchdog 12 power and reset control 12 power down mode 12 hardware reset generation 13 system error status register 13 discrete i/o 14 digital system test interface 15 microprocessor interface 15 general interface timing 15 write cycle to read cycle timings 15 write cycle to write cycle timings 15 notes about interface timing constraints 15 arm system mode 17 address map 17 control signals 17 arm system timing 17 wait state generation 17 debug (abort) function 20 standard interface mode 20 control signals 21 motorola style interface 21 intel 80186 style interface 21 intel 486 style interface 21 reset 21 register addressing 21 controlling the GP2021 22 search operation 22 carrier dco programming 22 code dco programming 22 code generator programming 22 reading the accumulated data 22 search on other code phases 22 data bit synchronisation 22 reading the measurement data 22 preset mode 23
3 GP2021 interrupts 23 signal path delay (introduced by hardware signal processing) 23 integrated carrier phase measurement 23 timemark generation 24 GP2021 register map 25 correlator registers 26 tracking channel registers 27 accum_status_a 28 accum_status_b 28 accum_status_c 28 chx_accum_reset 29 chx_carrier_cycle_counter 29 chx_carrier_cycle_high 29 chx_carrier_dco_incr_high 29 chx_carrier_dco_phase 29 chx_code_dco_incr_high 30 chx_code_dco_phase 30 chx_code_dco_preset_phase 30 chx_code_phase 30 chx_code_slew 30 chx_epoch_check 31 chx_epoch 31 chx_epoch_count_load 31 chx_i_track, chx_q_track, chx_i_prompt,chx_q_prompt 31 chx_satcntl 31 meas_status_a 33 multi_channel_select 33 prog_accum_int 33 prog_tic_high, prog_tic_low 34 reset_control 34 status 35 system_setup 35 test_control 35 timemark_control 36 x_dco_incr_high 37 peripheral functions registers 37 real time clock and watchdog 37 rtc_ls, rtc_2nd, rtc_ms 37 clock_reset 37 watchdog_reset 37 duart 38 config_a, config_b 38 status_a, status_b 38 reset_a, reset_b 38 tx_data_a, tx_data_b, rx_data_a, rx_data_b 38 tx_rate_a, tx_rate_b 39 system control 39 wait_state 39 system_config 39 system_error_status 39 chip_revision 39 data_retent 40 general control 40 io_config 40 test_config 41 data_bus_test 41 absolute maximum ratings 41 electrostatic discharge protection (esd) 41 crystal specification 41 electrical characteristics 42 pin types 44 timing characteristics 47 package details 64 detailed description of registers 25
4 GP2021 typical gps receiver fig. 2 shows a typical gps receiver employing a gp2010 rf frontCend, a GP2021 correlator and an arm60 32 bit risc microprocessor. a single front end may be used, since all gps satellites use the same l1 frequency of 1575.42 mhz. however, in order to achieve better sky coverage, it is sometimes desirable to use more than one antenna. in this case, separate front ends will be needed. the rf section, gp2010, performs down conversion of the l1 signal for digital baseband processing. the resultant signal is then correlated in the GP2021 with an internally generated replica of the satellite code to be received. individual codes for each channel may be selected independently to enable acquisition and tracking of up to 12 different satellites simultaneously the results of the correlations form the accumulated data and are transferred to the microprocessor to give the broadcast satellite data (the navigation message) and to control the software signal tracking loops. the GP2021 can be interfaced to one of two styles of front end. in real_input mode, the front end supplies either a 1 (sign) or 2 (sign and magnitude) bit signal to either the sign0/mag0 or sign1/mag1 inputs of the GP2021. alteratively, in real_input mode, 2 separate front ends can be connected to a single GP2021 and selected under software control. the gp2015 and gp2010 are real_input mode front ends. in complex_input mode, the front end is required to supply inCphase (i) and quadrature (q) signals to the sign0/mag0 and sign1/mag1 inputs respectively. hence, only a single front end can be used with each GP2021 in complex_input mode. gp2010 sign mag sampclk clk_t clk_i pll_lock 10mhz tcxo tx/rx serial comms port accum_int,meas_int 12 channel correlator wren read micro_clk peripheral functions memory control memory control data addr arm60 GP2021 l1 antenna fig. 2 block diagram of typical arm based receiver pin description all v ss and v dd pins must be connected in order to ensure reliable operation. any unused inputs must be tied high or low. the table below describes the pin functions in real_input mode and assumes a master clock input frequency of 40mhz. those pins whose functions differ in complex_input mode are described at the end of the table. note that those pin names containing a / have dual functionality between arm system and standard interface modes. the pin mnemonic for arm system mode always precedes the /. pin no signal name type description arm system mode description standard interface mode 15, 35, v ss - ground pin 56, 69, 72 14, 34, v dd + power supply to device. 55, 67, 74 1 multi_fn_io i/o multiCfunction input / output. its function is configured by the io_config register. after a GP2021 reset it acts as the digital system test enable input. it can also be configured as a discrete output, or a discrete input if certain conditions are met. can be configured as the trigger input to the debug block in arm system mode.
5 GP2021 pin no signal name type description arm system mode description standard interface mode 2 power_good i power monitor input. high for normal operation. low forces the GP2021 into power down mode. 3 nreset_op o system reset output (active low). lasts for 4 micro_clk cycles after all reset conditions have cleared. 4 narmsys i processor mode selection input. when low, this input selects arm system mode. when high, standard interface mode is selected. 5 xin i crystal input connection to real time clock. 6 xout o crystal output connection from real time clock. 7 txa o transmit data output from channel a of the dual uart. 8 txb o transmit data output from channel b of the dual uart. 9 rxa 1 receive data input to channel a of the dual uart. this pin acts as a master clock input in digital system test mode. 10 rxb i receive data input to channel b of the dual uart. this pin acts as the real time clock reset in digital system test mode. 11 nrom / nc o rom chip select output (active low). unused output. (do not connect.) 12 neeprom / nc o eeprom chip select output (active low) unused output. (do not connect.) 13 nspare_cs / nc o spare chip select output (active low). unused output. (do not connect.) 16 nram / nc o ram chip select output (active low). unused output. (do not connect.) 17 nw0 / nc o byte 0 write strobe output (active low). unused output. (do not connect.) 18 nw1 / nc o byte 1 write strobe output (active low). unused output. (do not connect.) 19 nw2 / nc o byte 2 write strobe output (active low). unused output. (do not connect.) 20 nw3 / nc o byte 3 write strobe output (active low). unused output. (do not connect.) 21 nrd / nc o read data strobe output (active low). unused output. (do not connect.) 22 arm_ale / nc o ale output to the microprocessor unused output. (do not connect.) (active high). controls the transparent latches at the microprocessor address outputs. 23 dbe / nc o data bus enable output to the unused output. (do not connect.) microprocessor. when low, places the microprocessor data bus drivers in a high impedance state. 24 accum_int o a free running interrupt to the microprocessor. it allows control of data transfer between the accumulators in the correlator and the microprocessor. it is active low when configured for arm system mode or motorola mode and is active high in intel mode. 25 meas_int o an interrupt to the microprocessor. it allows control of measurement data transfer between the correlator and the microprocessor. it is active low when configured for arm system mode or motorola mode and is active high in intel mode. 26 nbw / wrprog i byte/word input from the writeCread program input. in intel microprocessor. low indicates a byte mode, high selects 486 style transfer, and high a word transfer. interface and low 186 style. unused in motorola mode 27 nmreq / discip2 i memory request input from the multiCpurpose discrete input. microprocessor. low indicates that the microprocessor requires a memory access during the following cycle. 28 nopc / nintelmot i opcode fetch input from the high selects motorola mode and microprocessor. low indicates that an low intel mode. instruction is being fetched and high that data is being transferred. 29 nrw / discip3 i read/write select input from the multiCpurpose discrete input. microprocessor. low indicates a read cycle and high a write cycle. 30 mclk / nc o microprocessor clock output unused output. (do not connect.) (nominally 20mhz). its phases can be stretched under control of the microprocessor interface.
6 GP2021 pin no signal name type description arm system mode description standard interface mode 31 abort/ micro_clk o abort output to the microprocessor. 20mhz clock output. provides a generates a valid arm data abort 20mhz clock with a 1:1 sequence, triggered by a rising edge mark-to-space ratio at multi_fn_io if this function is enabled. 32 discio i/o multiCpurpose discrete input / output. after a GP2021 reset it is configured as an input. 33 a22 / read i address input from the microprocessor. read input from the a<22:20> are decoded to select the microprocessor. in intel mode address space partitioning. it is the active low read strobe. in motorola mode it is the read (high)/write (low) select line. 36 a21 / ncs i address input from the microprocessor. GP2021 chip select input a<22:20> are decoded to select the (active low). address space partitioning. 37 a20 / wren i address input from the microprocessor writeCread strobe input from a<22:20> are decoded to select the the microprocessor. in intel address space partitioning. mode it is the active low write strobe. in motorola mode it is the active high write-read strobe. 38 C 45 a<9:2> i address inputs <9:2> from the microprocessor. these allow register selection. 46 a1 / ale_ip i address input 1 from the address latch enable input microprocessor. a<1:0> are decoded from microprocessor (active to provide individual byte write high) selection via nw<3:0>. 47 a0 / nreset_ip i address input 0 from the reset input (active low). microprocessor. a<1:0> are decoded to provide individual byte write selection via nw<3:0>. 48C 54, d<0:15> i/o bidirectional data bus. 57C65 66 pll_lock i pll lock indicator input from rf section. when high this signa indicates that the pll within the rf section is in lock and the master clock inputs have stabilised. 68 discop o multiCpurpose discrete output. 70 clk_t i master clock input (40mhz). 71 clk_i i inverted master clock input. 73 sampclk o sample clock output to the front end. provides a 5.714mhz clock with a 4:3 markCtoCspace ratio. 75 nbram / discip4 i battery backed ram select input. multiCpurpose discrete input. defines the state of the nram output in power down mode. 76 sign0 i sign0 input from the rf section. 77 mag0 i mag0 input from the rf section. 78 sign1 i sign1 input from a second, optional, rf section. 79 mag1 i mag1 input from a second, optional, rf section. 80 discip1 i multiCpurpose discrete input.
7 GP2021 difference between real and complex_input mode the input mode is selected by thefront_end_mode bit in the system_setup register. it defaults to real_input mode at power up. the differences between real and complex input mode are summarised in the following table. description real_input mode complex_input mode recommended master clock frequency 40mhz 35mhz GP2021 internal clocking 1 7 ? 6 micro_clk 2 output frequency 20mhz 17.5mhz mark : space 1:1 1:1 pin no 76 sign 0 sign_i pin no 77 mag 0 mag_i pin no 78 sign 1 sign_q pin no 79 mag 1 mag_q input signal sampling rate 5.714mhz 5.833mhz sampclk output frequency 5.714mhz not available mark : space 4:3 (held low) ) notes. 1 the GP2021 interrupt and tic timebase dividers are clocked by this resulting clock. 2 the mclk output is derived from this signal. in arm mode the phases of mclk are stretched by the microprocessor interface block. functional description the GP2021 incorporates a 12 channel gps correlator, together with microprocessor support functions including a dual uart, a real time clock and memory control logic for the arm60 microprocessor. it can be configured for either arm system mode or standard interface mode. a block diagram of the GP2021 is shown in fig. 3. whilst in arm system mode the memory control logic allows an arm60 microprocessor to interface with the correlator, real time clock, dual uart and a variety of memory devices (i.e. sram, eprom, flash and eeprom), without the need for external glue logic. in standard interface mode the GP2021 allows most 16 and 32 bit microprocessors to interface with the correlator, real time clock and dual uart. more specifically, this mode allows the interface to be configured for either intel or motorola style microprocessor interfaces. in the functional description which follows the correlator is described first, followed by the peripheral functions. meas_int d<15:0> rxa, rxb txa, txb xin xout sign, mag sampclk clk_t , clk_i power_good pll_lock micro_clk nreset_ip nreset_op a<22:20> arm60 interface memory interface ale_ip ncs wren read narmsys a<9:0> nintelmot wrprog 12 channel correlator gps power & reset control dual uart real ?time clock control bus data bus microprocessor interf ace arm system standard interface accum_int fig. 3 : GP2021 block diagram
8 GP2021 12 channel correlator fig. 4 shows a block diagram of the correlator. it consists of the following blocks: clock generator the clock generator block divides the frequency of the master clock clk_t/clk_i by 6 or 7 to give the internal multiC phase set of clocks. when in real_input mode clk_t/clk_i will normally be a 40mhz clock, which is divided by 7. when in complex_input mode it will normally be at 35mhz which is divided by 6. the sampclk pin is an output giving a 4:3 markCtoCspace ratio clock at 40 mhz / 7 (= 5714mhz) in real_input mode. the clock generator also produces the micro_clk signal at half the master clock frequency (20 mhz for real_input mode, 17.5 mhz for complex_input mode) with a 1:1 markCtoCspace ratio. this signal is output on the micro_clk pin in standard interface mode. however, its main purpose is that of a synchronising clock to the memory control logic in arm system mode and it is from this that the processor clock output, mclk, is derived. timebase generator the timebase generator produces 4 important timing signals: accum_int, tic, meas_int and timemark. accum_int is an interrupt provided to control data transfer between the correlator accumulators and the microprocessor. it may be detected by means of the accum_int output or by reading the accum_status_a register (where bit 15 is a flag indicating that accum_int has occurred since the previous read of this register). accum_int is cleared by reading accum_status_a. after powerCup this interrupt occurs every 505.05 m s. its period can subsequently be changed in one of 3 ways: 1) toggling the front_end_mode bit of the system_setup register, 2) toggling the interrupt_period bit of the system_setup register, or 3) writing directly to the prog_accum_int register. see section detailed description of registers on page 25 for more information. tic is an internal signal with a default period of 99999.90 m s. it is used to latch measurement data (epoch count, code phase, code dco phase, carrier dco phase fig. 4 correlator block diagram and carrier cycle count) of all 12 channels at the same instant. its period can subsequently be changed, by writing to the prog_tic_high and prog_tic_low registers, or toggling the front_end_mode bit of the system_setup register. meas_int is a signal derived from the tic counter. it may be used by the microprocessor as a software module switching interrupt either by using the meas_int output or by reading the accum_status_b or meas_status_a register. meas_int is activated at each tic and 50 ms before each tic so long as the tic period is greater than 50 ms. if the tic period is less than 50 ms, meas_int is activated only at each tic. it is cleared by reading either the accum_status_b or meas_status_a register, depending upon the meas_int_source bit of the system_setup register. timemark is also derived from tic and may be output on one of the discrete output pins. this signal is intended to be used as an accurate 1 pulse per second timing reference, aligned to utc (universal time coCordinated system), with a pulse width of 1ms. timemark has two methods of operation but in both tracking module channel 0 tracking module channel 1 tracking module channel 2 tracking module channel 3 tracking module channel 11 register selects address decoder a<9:2> 32 bit bus d<15:0> control bus interface status registers system status multi phase clocks clock generator clk_t clk_i sampclk micro_clk meas_int accum_int timebase generator tic internal sampclk latched sign0 & mag0 latched sign1 & mag1 sample latch sign0 & mag0 sign1 & mag1 v dd power supply v ss bits
9 GP2021 cases timemark rising edges are generated coCincident with the rising edges of tic. therefore, for timemark to be aligned with utc, tic must be aligned with utc. this is done by modifying the tic period for a single tic cycle, then setting it back to its original value, thus slewing the phase of tic. timemark may be generated by setting the timemark_arm bit in the timemark_control register, in which case the next tic will generate a rising edge at timemark and clear the timemark_arm bit. alternatively timemark may be generated as a programmable integer number of tics, again under the control of the timemark_control register. status registers there are four status registers (accum_status_a, _b, _c and meas_status_a). these contain flags associated with the accumulated and measurement data held on each of the 12 channels. some system level status bits also appear in these registers. sample latches the sample latches synchronise data from the front end to the internal sampclk. in real_input mode the down converted satellite signal can be sampled at the output of the front end by sampclk. this data is then input to the GP2021 as 2 bit data on either the sign0, mag0, or sign1, mag1 inputs, where it is reCsampled at the next rising edge of sampclk. these signals are then distributed to the 12 tracking modules. when a gp2015 or gp2010 front end is used, the data represents a bandClimited signal at an if centered on 4.309mhz. sampling at 5.714mhz aliases it to an if of 1.405mhz. in complex_input mode, the down converted satellite signal is applied direct to the GP2021 at its sign0, mag0, sign1, mag1 inputs, which act as inCphase sign, inCphase magnitude, quadrature sign and quadrature magnitude respectively. these signals are sampled at 5.833mhz within the correlator and then passed to the tracking modules. address decoder the address decoder performs address decoding for the correlator. bus interface the bus interface controls the transfer of data between the external 16 bit wide data bus and the internal 32 bit data bus. apart from the code and carrier dco increment values, all data transfers are 16 bits wide. write operations to the code and carrier dcos are 32 bit data transfers, in which the high 16 bit word must be written immediately before the low 16 bit word. note that the write cycle to write cycle delay of 300 ns referred to in the microprocessor interface does not apply between the first and second write cycles for 32 bit dco data transfers. for further information see the microprocessor interface section. tracking modules the tracking modules are 12 identical signal tracking channels numbered ch0 to ch11, each with the block diagram shown in fig 5. these blocks generate the data used to track the satellite signals. there is no overwrite protection mechanism on this data. for further information see the section on controlling the GP2021. each tracking channel can be individually programmed to operate in either update or preset mode. update mode is the normal mode of operation. preset mode is a special mode of operation where writes to certain registers are delayed until the next tic to allow synchronisation of registers and presetting of the code dco phase. for further information see the preset mode section in the detailed operation of the GP2021. the individual subCblocks in the tracking modules are: carrier dco the carrier dco, which is clocked at the sampclk frequency, is used to synthesise the digital local oscillator signal required to bring the input signal to baseband in the mixer block, and must be adjusted away from its nominal value to allow for doppler shift and reference frequency error. when used with the gp2015/gp2010 the nominal frequency of this signal is 1405396825 mhz (with a resolution of 42.57475 mhz) and is set by loading the 26 bit register chx_carrier_dco_incr. this very fine resolution is needed so that the dco will stay in phase with the satellite signal for an adequate time. the carrier dco phase cannot be directly set, but must be adjusted by altering the frequency. the carrier dco outputs are 4 level, 8 phase sinusoidals with the following sequences over one cycle: as the clock to the dco is normally less than 8 times the output frequency, not all phases are generated in every cycle. with a typical clock frequency of 5714 mhz and an output frequency of 1405 mhz there are only around 4 phases per cycle. these will slide through the cycle as time progresses to cover all values. code dco the code dco is similar to the carrier dco block. it is also clocked at the sampclk frequency and synthesises the oscillator required to drive the code generator at twice the required chipping rate. the nominal frequency of the output is 2046 mhz, to give a chip rate of 1023 mhz and is set by loading the 25 bit register chx_code_dco_incr. it is programmed with a resolution of 8514949 mhz when used with a gp2015/gp2010 front end. the very fine resolution is again needed to keep the dco in phase with the satellite signal. the code dco phase can only be set to the exact satellite phase in preset mode. in update mode, it must be aligned with the satellite phase by adjusting its frequency. carrier cycle counter the carrier cycle counter is 20 bits long, and keeps a count of the number of cycles of the carrier dco between tics. this is not needed for a basic navigation system but may be used to measure the range change (deltaCrange) to each satellite between tics. the delta ranges can be used to smooth the code pseudoCranges. for finer detail the carrier dco phase may also be read at each tic to give the fractional part of the cycle count or deltaCrange. c/a code generator the c/a code generator generates the selected gold code for a gps satellite (1 to 32), a ground transmitter (pseudolite, 33 to 37), an inmarsatCgic satellite (201 to 211) or a glonass satellite. a gold code is selected by writing a specific pattern of 10 bits, as listed in the section detailed description of registers, to the chx_satcntl register, or by setting the gps_nglon bit to low for the glonass code. two outputs are generated to give both a prompt and a tracking signal. the tracking signal can be set to one of four modes: early (one half chip before the prompt signal), late (one half chip behind), dithered (toggled between early and late every 20ms) or earlyCminusClate (the signed difference). the output code is a sequence of +1s and C1s for all code types except earlyCminusClate where the result can also destination arm i lo q lo sequence C1+1+2+2+1C1C2C2 +2+2+1C1C2C2C1+1 table 1 carrier dco outputs
10 GP2021 be a 0. to avoid having an unused lsb in the accumulators, the values in earlyCminusClate mode are halved from the +2, 0, C2 that results from the calculation (+1 or C1) C (+1 or C1) to +1, 0, C1. this must be considered when choosing thresholds in the software, as the correlation results will be exactly half of the values otherwise expected. at the end of every code sequence (1023 chips in gps mode or 511 chips in glonass mode) a dump signal is generated to latch the accumulated data for use by the signal tracking software. each channel is latched separately, as the satellite signals are not received in phase with each other. source selector in real_input mode the source selector selects which input signal pair to use (sign0/mag0 or sign1/mag1). in complex_input mode sign0/mag0 are passed to the inC phase arm and sign1/mag1 to the quadrature arm. the data is treated as having the values shown in table 2 below (in both modes): carrier mixers the carrier mixers multiply the digital input signal by the carrier dco digital local oscillator to generate a signal at baseband. in real_input mode both i and q carrier dco phases are directed to the appropriate mixers. in complex_input mode a single inCphase carrier dco output is used in both mixers since the input signal is already in i and 16 bit accumulate and dump ?q_tracking 16 bit accumulate and dump ?q_prompt code slew c/a code generator code phase counter code dco epoch counters dump accums, code phase, etc 16 bit accumulate and dump ?i_prompt 16 bit accumulate and dump ?i_tracking carrier cycle counter carrier dco i 1, 2 source selector sign 0 and mag 0 sign 1 and mag 1 select source and select mode in and out data busses code mixer carrier mixer 1, 2, 3, 6 3 lo q lo i lo 1 1, 0 or 1, fig.5 tracking module block diagram sig 0 0 1 1 mag 1 0 0 1 value -3 -1 +1 +3 table 2 sign/mag values q form. the mixing of the carrier dco outputs with the input signal produces a baseband signal which can have the values 1, 2, 3 and 6. code mixers the code mixers multiply the i and q baseband signals from the carrier mixers with both the prompt and tracking local replica codes to produce 4 separate correlation results. the correlation results are passed to the accumulate and dump blocks for integration. accumulate and dump the accumulate and dump blocks integrate the mixer outputs over a complete code period of nominally 1ms. there are 4 separate 16 bit accumulators for each channel. these represent the correlation of the i and q signals with the prompt and tracking codes, over the integration period. there is no overwrite protection mechanism on these registers so the data must be read before the next dump. code phase counter the code phase counter counts the number of halfCchips of generated code and stores this value in the chx_code_phase register on each tic. code slew counter the code slew counter is used to slew the generated code by a number of half chips in the range 0 to 2047. in update mode the slew occurs following the next dump. in preset mode it occurs at the next tic. all slew operations are relative to the current code phase. the code slew counter must be written to each time a slew is required. during the slewing process the accumulators for the channel being slewed are inhibited so that the first result is valid. if a slew is written while a channel is disabled it will occur as soon as the channel is enabled.
11 GP2021 epoch counter the epoch counters keep track of the number of code periods over a 1 second interval. this is represented by a 5 bit word for the number of 1 ms integration periods (0 to 19), plus a 6 bit word containing the number of 20 ms counts (0 to 49). the epoch counters can be preCloaded to synchronise them to the data stream coming from the satellite. this value will be transferred immediately to the counter when in update mode, or after the next tic if in preset mode. the epoch counter values are latched on each tic into the chx_epoch register. in addition the instantaneous values are available from the chx_epoch_check register. peripheral functions the following section describes the dual uart, real time clock and watchdog, power and reset control and discrete i/o blocks. dual uart a dual uart is included for serial communications. it has 2 identical blocks, uart_a and uart_b, each containing separate transmit and receive channels. the parity and separate transmit and receive baud rate can be configured independently for each uart. each uses a polled processor interface and each transmit and receive channel has an 8 byte deep fifo. for further information on the uart registers refer to the detailed description of registers and the GP2021 register map. a typical serial data stream is shown in fig. 6. the parity bit is optional and if no parity is selected the time slot for it is removed from the data stream and the stop bit follows immediately after the last data bit in both transmit and receive directions. note that the lsb is always preceded by a start bit. table 3 shows possible uart configurations. last start d8 d9 d10 d11 d12 d13 d14 d15 p stop first lsb msb parity (optional) fig. 6 serial data waveform parameter value start bits 1 bit low data bits 8 bits logic 0 = low logic 1 = high stop bits 1 bit high parity odd/even/none flow control none transmit fifo depth 8 bytes receive fifo depth 8 bytes fifo speed transmit fifo write rate and receive fifo read rate maximum is one byte per 230ns. the maximum buffer through delay is 2 m s. data rate 300, 600,1.2k, 2.4k, 4.8k, 9.6k, 19.2k, 38.4k and 76.8k baud. transmit and receive rates individu-ally configured. table 3 uart functionality receiver the incoming data streams on rxa, rxb are sampled by a clock at nominally 20 times the data rate, to search for an incoming start bit. once the receiver is synchronised to the data stream, each data bit is sampled only at its nominal centre to avoid errors due to slow or noisy bit edges. the receiver will resynchronise to each start bit to prevent the accumulation of phase errors. only valid data (having correct start, stop and parity bits) will be stored in the receiver fifo. if a received word contains a parity or framing (start/stop bit) error, the appropriate flag bit will be set in the status register. if too many valid data words are received for the fifo to hold, the excess will not be written into the fifo, and an overflow bit will be set in the status register. when receiving a continuous transmission, the start bit of one word will follow immediately after the stop bit of the preceding word. at lower word rates, a high is expected between words. the receiver will accept data with a baud rate error of up to 1%. transmitter data is transmitted on pins txa and txb. in continuous transmission, the start bit of one word will follow immediately after the stop bit of the preceding word. at lower word rates, a high is sent between words. if too many data words are written by the microprocessor to the uart for the transmitter fifo to hold, the excess will not be stored. the uart will resume normal operation as soon as space becomes available. to avoid data loss, the software should limit the transmit data rate by either: keeping track of the number of bytes sent and the time to transmit them, or should read the status register and stop writing when the full bit is set.
12 GP2021 reset it is possible for the software to reset either uart independently via the reset_chx registers. a hardware reset affects both uarts. during a uart reset, the contents of all control, and status registers will be cleared. in addition the transmit and receive fifos will be emptied and the tx outputs will be held low. channel loopback for system test purposes, a loopback facility is provided for each channel, controlled by the configuration registers. in loopback, the tx output is set high. real time clock (rtc) and watchdog this block consists of a 32.768khz crystal oscillator, a fixed divider, a 24 bit counter, a watchdog function and three 8 bit data registers. xin and xout are the crystal in and crystal out connections to the oscillator circuit. a recom- mended crystal oscillator circuit is shown in fig. 7. when the real time clock v ss is not being used, xin must be tied low. the first divider is a fixed divide by 32768 giving a 1 hz output. the counter then counts seconds, giving a maximum time of 194 days. the time is output in three 8 bit registers with the data being latched when a read is performed to the ls register (the register holding the least significant byte of the clock data). on reaching its maximum count, the count is frozen (i.e. all 1s), until being reset. in power down mode the real time clock continues to run, but access to the data registers is not allowed. when normal power is restored, the software can determine the elapsed time whilst in power down mode, thereby assisting in estimating the current position of gps satellites and so reducingtimeCtoCfirstCfix. the watchdog generates a system reset (see power and reset control) if the watchdog reset address has not been written to for a period of approximately 2s. the watchdog function is inhibited whilst in power down mode and can be disabled via a bit in the system configuration register.the software is able to reset the real time clock and watchdog via the clock reset and watchdog reset registers respectively. in addition the watchdog is reset during a system reset. for further information on the registers refer to the section detailed description of registers. power and reset control this block performs 2 functions: power control and system reset generation power down mode in order to allow power conservation within a battery backup system, the GP2021 provides a power down mode, in which the supply voltage may drop to a minimum of 2.2v, thereby minimising the supply current. in this mode all functions within the GP2021 are disabled except for the real time clock. the GP2021 is placed in power down mode by taking the power_good pin low. in arm system mode with the nbram pin held low, the initiation of power down mode is delayed until just after a falling edge of micro_clk so as not to corrupt battery backed ram. fig. 8 shows a suggested circuit implementation. table 4 shows output logic levels in power down mode. in power down mode all inputs and i/os except power_good and xin are internally switched to known logic levels to prevent extraneous switching from causing excessive power consumption, and may therefore be left floating. all the i/o pins (d<15:0>, multi_fn_io and discio) have their output drivers driven to the high impedance state. xin xout 22pf 22pf crystal 10m v ss v ss 680k 32.768khz fig. 7 recommended crystal oscillator circuit battery supply d1 supply +5v c1 voltage sensor GP2021 power_good c2 v dd t2 r1 r2 t1 v ss v ss fig. 8 : suggested battery backup configuration
13 GP2021 pin name logic level nw<3:0> / nc low nrd / nc low nram low (standard interface mode) nram nb ram (arm system mode) nrom / nc high impedance nspare_cs/nc high impedance neeprom / nc high impedance txa,txb low accum_int high impedance pin name logic level meas_int high impedance a bort / micro_clk low mclk / nc low arm_ale / nc low dbe / nc low nreset_op low discop high impedance sampclk low xout active table 4 : output logic levels in power down mode hardware reset generation the manner in which a hardware reset occurs depends on whether the GP2021 is in arm system mode or standard interface mode. during a hardware reset, the nreset_op pin is taken low and the reset signal is applied within the GP2021 to all blocks except the real time clock. there are 3 sources of hardware resets common to both arm system and standard interface modes, with an additional source in standard interface mode: power_good: a hardware reset will occur if this pin is taken low, as shown in fig. 9. the purpose of this input is to detect a power failure. if the nbram pin is held low in arm system mode, the internal power down mode is not entered until about 6ns after the falling edge of micro_clk, otherwise it is entered immediately. this allows for ram write cycles to complete sensibly when battery backedCup ram is used, with no corruption of ram data. watchdog: an expiry of the watchdog will result in a hardware reset as shown in fig. 10. this reset will clear the watchdog whose timeCout period is 2C3 seconds. pll_lock: the pll_lock pin is used to indicate (when high),that the phase locked loop in the rf front end, which generates the master clock, is in lock. this signal is filtered within the GP2021 and the reset state associated with it is only deCactivated if the pll_lock input has been high for approximately 50 ms as shown in fig. 11. nreset_ip: in addition to the 3 reset sources described above, an active low nreset_ip pin is available in standard interface mode if the system resets are to be generated externally. fig. 12 shows a nreset_ip generated reset. note that the nreset_op pin will go high 4 micro_clk cycles after all hardware reset sources have cleared. this fulfills the reset requirements of the arm60 microprocessor. for information on the state of the registers following a hardware reset refer to the detailed description of registers section. system error status register this allows the software to determine whether the source of a hardware reset was from a power failure, a pll_lock failure, watchdog timeout or from an external reset in standard interface mode. for further information refer to the detailed description of registers section. micro_clk/ nreset_op power_good 4 cycles mclk power down mode fig. 9 : power_good hardware reset generation (narmsys = 0, nbram =0) micro_clk/ nreset_op watchdog 122 s 4 cycles mclk fig. 10 : watchdog hardware reset genera-
14 GP2021 pll_lock nreset_op micro_clk 4 cycles mclk 50ms nreset_ip nreset_op micro_clk 4 cycles fig. 11 : pll_lock hardware reset generation fig. 12 : nreset_ip hardware reset generation discrete i/o the GP2021 contains a number of pins which may be used as discrete inputs or discrete outputs for general purpose system monitoring and control applications. the actual pins which may be used for each function vary according to the application and the interface mode of the GP2021.table 5 shows a list of possible discrete inputs and outputs and the modes in which they may be used. the level on all discrete inputs can be read from the io_config register. the status of the discip pin may also be read from accum_status_b. the discrete outputs are controlled via either the system_setup or io_config registers. discrete inputs pin name read location conditions for use as discrete input nrw/discip3 io_config standard interface mode. nopc/nintelmot io_config arm system mode (debug disabled). nmreq/discip2 io_config standard interface mode. nbw/wrprog io_config motorola mode only. discio io_config discio configured as discrete input. nbram/discip4 io_config standard interface mode. multi_fn_io io_config multi_fn_io configured as discrete input. sign0, mag0 io_config single real input mode (gp2010 or gp2015) front end using sign0, mag0. sign1, mag1 io_config single real input mode (gp2010 or gp2015) front end using sign1, mag1. discip1 io_config always available C dedicated discrete input. accum_status_b rxa io_config uart channel a not used. rxb io_config uart channel b not used. discrete outputs pin name configuration possible outputs location discop system_set_up high, low, ch0 dump, timemark, 100khz square wave, scan out. discio io_config high, low, timemark, 100khz square wave. multi_fn_io io_config high, low, timemark, 100khz square wave. table 5 : discrete input/output configuration
15 GP2021 digital system test interface the GP2021 contains a digital system test mode to allow testing of the digital section of the system board. provided that the multi_fn_io pin is high, this mode is enabled subsequent to a hardware reset or a write of specific data to the io_config register. the enabling of digital system test mode has 3 effects: (1) the master clock inputs, clk_t and clk_i, are replaced by the signal on the rxa pin. this allows the GP2021 to be clocked synchronously with the board tester which is relevant in arm system mode where the GP2021 produces the main processor clock to the arm60. (2) the rxb pin becomes the active high rtc reset input. this is mainly intended for factory testing of the GP2021, allowing the rtc to be reset on power up, but may also be used to disable the rtc and watchdog circuits in this mode. (3) the pll_lock input and its associated 50ms delay as a reset source is overridden. this removes the dependency on the presence of the front end circuit. microprocessor interface the microprocessor interface of the GP2021 is compatible with most 16 and 32 bit microprocessors. it can be configured for either arm system mode or standard interface mode by means of the narmsys pin. in standard interface mode, two mode control pins nintelmot and wrprog are provided. nintelmot selects between intel and motorola style interfaces, with wrprog selecting either intel i486 or 80186 style interfaces. see table 6 for more details. narmsys nintelmot wrprog mode processor 0 x x arm system arm60 1 1 x standard interface motorola style 1 0 0 standard interface intel 80186 style 1 0 1 standard interface intel 486 style table 6 microprocessor interface configuration. general interface timing in addition to the detailed timings associated with individual read and write cycles ( see electrical characteristics section), the internal architecture of the correlator also imposes limits on cycle to cycle timings (in particular write to write cycle and write to read cycle). for a simple microprocessor interface, it must be ensured that no attempts are made to access the correlator for the 300ns following the end of a correlator write cycle in real_input mode, or 314ns in complex_input mode. however, if the controlling software is to be allowed to write rapidly to the correlator (e.g. block writes), then a more complex bus interface (which inserts wait states) will be required. note that this limitation only applies after correlator writes, not peripheral function writes, and also does not apply to writes to the correlator x_dco_incr_high address. the correlator section of the GP2021 uses a multiCphase clock internally, and the correlator registers load on specific clock phases. at the end of a write cycle, the falling edge of the internal write strobe latches both the relevant address and data bits. this data is then loaded from the internal data bus to the relevant register at some time during the following 300ns for real_input mode or 314ns for complex_input mode. a write cycle to the correlator with no writes in the preceding 300ns (314ns) may be performed immediately, so long as the detailed signal timings are met. however, subsequent read or write cycles to the correlator after this write cycle may need to be delayed if they would modify the internal address or data lines. correlator read cycles with no write cycles in the preceding 300ns (314ns) are selfCcontained, and do not delay subsequent cycles. an isolated read cycle requires only sufficient wait states to meet the detailed signal timings. write cycle to read cycle timings as described previously, the internal write cycle of the correlator takes 300ns (314ns). only once the write cycle is complete will the correlator address decoders switch to decoding the current address. the correlator uses a preC charged internal data out bus and hence the decoded address lines must be stable before the internal bus drivers are enabled (when the read strobe goes high). consequently, the read strobe must be held low until some time after the end of the 300ns (314ns) internal write cycle, to allow sufficient internal address setup time. for the exact timing requirements see the electrical characteristics section. write cycle to write cycle timings the internal write cycle of the correlator takes 300ns (314ns) after the falling edge of the write strobe. during this time the write internal address and data busses (latched by write) must not be modified. if a second write follows the first, the second write cycle must be delayed such that it ends no earlier than 300ns (314ns) after the end of the previous write. the end being a falling edge on the internal write strobe. the specific interface signal timings must also be met. notes about interface timing constraints it should also be noted that these timings need only be met for correlator accesses, not support function accesses, since these utilise selfCcontained write cycles and are not clocked by the multiCphase clocks. in addition, writes to the correlator register x_dco_incr_high need not incur subsequent delays since writes to this location do not instigate an internal write cycle. a write to this address must always be followed by a write to either a chx_carrier_dco_incr_low or a chx_code_dco_incr_low register and it is this second associated write which instigates the internal write cycle. in arm system mode all these timing requirements are handled by the internal memory manager.
16 GP2021 wren read ncs a<9:2> d<15:0> read read read write delayed w rite delayed read note: op and ip are with respect to the GP2021. op denotes a GP2021 output, ip denotes a processor output. op op ip op op ip 300ns (314ns) 300ns (314ns) fig.13 correlator bus timing - write to write and write to read timings arm60 GP2021 memory nram nrom neeprom nspare_cs nw<3:0> nrd d<15:0> a<9:2> a<19:10> dbe arm_ale mclk nrw nmreq nbw d<15:0> a<9:2> a<22:20>, a<1:0> nopc abort a<19:10> (nreset_op , accum_int and meas_int not shown) fig.14 arm system mode note that the exact number of wait states which need to be inserted after a correlator write is not fixed. if the processor were to perform a correlator write then spend 400ns accessing a different peripheral, subsequent correlator reads and writes would incur no additional delay. it is anticipated that correlator wait states will be generated by either one or two external counters, preset on the falling edge of a correlator write, and which then count down to zero. only once the counter has reached zero may the next correlator access either complete (write) or start (read). a series of correlator reads and writes are shown in fig.13.
17 GP2021 arm system mode arm system mode, as shown in fig 14, allows the GP2021 to be interfaced with an arm60 microprocessor and external memory devices (i.e ram, rom, eeprom, eprom, flash) without the need for external glue logic. address map both the GP2021 and external memory devices are memory mapped into 1 mbyte segments by a<22:20> as shown in table 7. decoded a22 a21 a20 device selected output pin 0 0 0 rom nrom 0 0 1 ram nram 0 1 0 correlator 0 1 1 support functions 1 0 0 eeprom neeprom 1 0 1 user defined nspare_cs 1 1 0 not decoded 1 1 1 not decoded table 7 arm system map control signals the GP2021 uses the arm60 control signals nbw, nmreq and nrw to generate the processor clock mclk and the control signals arm_ale and dbe to match the timing requirements of the various memory devices . the memory interface is via the memory chip select lines ( nram, neeprom, nrom and nspare_cs) , the read line (nrd) and the byte write select outputs ( nw<3:0> ). arm system timing the GP2021 timing diagrams for each of the memory interfaces ( eeprom, ram, rom, spare), and arm60 areshown in the section electrical characteristics. wait state generation to allow access to slow peripherals or memory, the clock (mclk) to the arm60 microprocessor may be stretched in either phase 1 (low) or phase 2 (high), thus allowing wait states to be introduced (where a wait state is defined as being one mclk period long). the GP2021 introduces one wait state for accesses to the real time clock, dual uart and system control registers, as shown in fig 15. correlator accesses, as shown in fig 19 incur one wait state; subsequent accesses being prevented from contravening the correlator requirements (see correlator functional description) by adding several wait states. in order to ensure compatibility with variety of memory devices, the rom interface is programmable with between one to three wait states, while the eeprom and spare interfaces can be programmed with between three to six wait states via the wait state register. for further information on the wait state register, refer to detailed description of registers. read and write cycles for the ram, eeprom (or spare) and rom interfaces are shown in figs 16C18. during a read cycle from flash memory, the output disable to data bus release time, could be greater than 25 ns. hence in order to avoid bus contention, the nominal period of mclk is stretched by 25 ns during the following cycle. the arm60 is able to perform either byte or word ( 4 bytes wide) writes to memory. all registers within the GP2021 are word aligned, with only write accesses to external ram being either byte or word aligned. the signal nbw is used to indicate either a byte or word write request, with a<1:0> performing byte selection. decoding of nbw and a<1:0> is performed by the microprocessor interface, with nw<3:0> being the byte write select outputs to memory. during a word write all four of the outputs nw<3:0> will be active. note that the register addresses for the correlator and support functions are as shown in the GP2021 register map.
18 GP2021 fig.15 peripheral functions write/read cycle fig.16 ram read/write cycle 20mhz internal mclk arm_ale nrw nmreq nbw dbe internal write internal read d<15:0> valid 1 w ait st ate valid clock a<22:20>, a<9:0> mclk note: this diagram assumes nmreq is low . 20mhz internal arm_ale nram nw0 nw3 nw2 nw1 d<15:0> dbe nrd nrw nbw valid valid valid valid valid clock a<22:20>, a<9:2> valid
19 GP2021 fig.17 rom (1 wait state) and eeprom/spare (2+1wait states) read cycles mclk note: nr w , nmreq and dbe are assumed to be low 20mhz internal clock arm_ale neeprom nrom nrd d<15:0> a<22:20>, a<9:0> fig.18 eeprom (or spare) write cycle mclk note: nbw and nr w are assumed to be high for this cycle 20mhz internal clock arm_ale a<22:20>, a<9:0> neeprom nw<3:0> dbe d<15:0>
20 GP2021 fig.19 correlator write and read cycles 20mhz internal clock mclk arm_ale dbe nrw internal write internal read a<22:20>, a<9:0> d<15:0> valid valid note: nbw is high and nmreq low valid debug (abort) function this is a feature designed to aid debugging and functions as follows:C in arm system mode, the multi_fn_io pin can be configured as a trigger input to the debug block via the io_config register (see detailed description of registers). in this mode a rising edge at the multi_fn_io pin will generate a valid arm data abort sequence at the abort pin as shown in fig. 20. standard interface mode this mode allows the GP2021 to be interfaced to most standard 16 and 32 bit microprocessors as shown in fig. 21. no memory control is provided, so external glue logic may be required in order to interface the microprocessor to memory. abort mclk multi_fn_io nopc nmreq fig.20 debug (abort) function
21 GP2021 control signals in standard interface mode (narmsys held high), the microprocessor interface of the GP2021 consists of two mode control pins, (nintelmot and wrprog), and the control signals themselves, (ale_ip, ncs, wren and read; the exact function of which is dependent upon the interface style selected). motorola style interface (nintelmot = 1, wrprog = x) the wrprog mode control pin is not used in motorola interface mode and should be tied high or low. the ale_ip (address latch enable input) pin is used to transparently latch the address lines a<9:2> to the GP2021. if these address lines are already latched externally, this pin may be tied high. note that the internal ale signal is inhibited during a read or write strobe so the address lines may be changed once the read or write strobe has become active. the wren pin acts as a write/read enable strobe (active high) with the read pin selecting either a read strobe (read = 1) or a write strobe (read = 0). in a similar way to the addresses being latched during a read or write strobe, the read signal is also latched during a data strobe and may be changed towards the end of the cycle. the ncs pin is an active low chip select used to gate out the internal read and write strobes. in standard interface mode, the GP2021 can best be visualised in terms of 3 signals, ale_int, wrstrobe_int and rdstrobe_int, the internal ale, write strobe and read strobe signals. in motorola style interface mode these signals are derived as follows: ale_int=ale_ip. (wrstrobe_int + rdstrobe _int) wrstrobe_int = ncs.wren.read rdstrobe_int = ncs.wren.read intel 80186 style interface ( nintelmot = 0, wrprog = 0) in the 80186 style interface mode the ale_ip acts as an address latch enable input ( as in motorola mode), used to transparently latch the address lines a<9:2> to the GP2021. similar to motorola mode, if the addresses are latched externally this pin may be tied high. whereas motorola mode used a single strobe input and a read/write level to denote read and write strobes, both intel modes use a pair of strobe inputs, one for reads, and one for writes. in this mode, read acts as the active low read strobe ( read =rdstrobe) and wren the active low write strobe ( wren= wrstrobe). ncs is the active low chip select used to gate out internal data strobes. ale_int=ale_ip wrstrobe_int = ncs.wren rdstrobe_int = ncs.read intel 486 style interface (nintelmot = 0, wrprog=1) the intel 486 style interface is similar to the 80186 style interface, with similar separate read and write strobes. some of the later intel microprocessors (notably the i486) have a very small delay between the rising edge of ale and the falling edge of the read or write strobes. due to the pre-charged nature of the dataCout bus of the correlator, the address inputs must remain stable throughout the read strobe, and the small delay from ale to read strobe would produce insufficient address setup times for correct operation. the 486 style interface mode removes this problem by gating both the read and write strobes such that they are inhibited until the falling edge of ale_ip. the ale_ip pin must not be tied high in 486 style interface mode. ale_int= ale_ip wrstrobe_int = ncs. wren. ale_ip rdstrobe_int = ncs. read. ale_ip reset the nreset_ip pin allows the GP2021 to be provided with an external system reset. for further information refer to system reset in standard interface mode. register addressing as shown in the GP2021 register map, register addresses differ from those in arm system mode. in particular in standard interface mode the GP2021 address bus interface is via a<9:2>, with ncs acting as its chip select input. the address pins a0, a1 in arm system mode now become the nreset_ip and ale_ip inputs. hence, depending upon the system configuration employed, a<9:2> of the GP2021 could be connected to the microprocessor address pins a<7:0>. fig.21 standard interface mode note: nreset_op , accum_int , and meas_int are not shown narmsys GP2021 wrprog nintelmot v or ncs ale_ip wren read micro_clk d<15:0> a<9:2> microprocessor decode v dd dd v or dd high address lines v ss v ss address logic
22 GP2021 controlling the GP2021 the following section describes typical methods for controlling the GP2021. these include: signal acquisition and tracking, carrier phase measurement and timemark generation. search operation to perform signal acquistion, the carrier frequency and code phase space needs to be searched until the signal is detected. the maximum carrier frequency excursion from its nominal value is defined by the maximum carrier doppler shift plus the maximum receiver clock error. the maximum code phase is defined by the (fixed) code length. typically, all code phases will be searched at a given carrier frequency before advancing to the next carrier frequency bin and repeating the code phase search. carrier dco programming the following registers: chx_carrier_dco_incr_high (or x_dco _incr_high),and chx_carrier_dco_incr_low are programmed in sequence with the relevant data according to the frequency bin being searched. it is always necessary to write to both the _high and _low registers. carrier dco programming will become effective as soon as the channel is released (made active). if the channel is already active, writes to chx_carrier_dco_incr_low are effective immediately. (a small delay of up to 175ns will occur, to allow synchronisation of the processor write operation to the chip operation.) code dco programming the chx_code_dco_incr_high (or x_dco_incr_high) and the chx_code_dco_incr_low registers are programmed in sequence with the relevant data according to the estimated code frequency offset. it is always necessary to write to both _high and _low registers. code dco programming will become effective as soon as the channel is released (made active). if the channel is already active, writes to chx_code_dco_incr_low are effective immediately. (a small delay of up to 175ns will occur to allow synchronisation of the processor write operation to the chip operation). code generator programming for each channel, the chx_satcntl register is programmed as follows: (i) set the sourcesel bit to select the input signal source. (ii) set the track_sel bits to set the tracking arm code to either early or late (with respect to the prompt arm). (iii) set the g2_load bits to select the required prn code. (iv) program the chx_code_slew register with the desired code phase offset. the slew operation will become effective upon chx_rstb release. the first dump will generate accumulated data for the channel and set the associated chx_new_accum_data status bit. (v) release the relevant chx_rstb bits of the reset_control register to make the channel active. when the code clock is inhibited (to slew the code phase) the integrate and dump module is held reset. it will start to accumulate correlation results only after the slew operation is completed. a search for a satellite on more than one channel may be performed using the multi channel addresses and different code slew values as appropriate. reading the accumulated data at each dump the corresponding chx_new_accum_data status bit is set in the accum_status_a register. the status register, together with all accumulation registers (chx_i_track, chx_q_track, chx_i_prompt, chx_q_prompt) are mapped into consecutive addresses. these can be read as a consecutive block, if required, after every accum_int interrupt. alternatively, the status registers may be polled. the accumulation registers are not overwrite protected, therefore the system must respond quickly when new data becomes available. whether or not it is necessary to process the accumulation at every dump is dependent upon the application. the order of reading them is optional, but ideally the chx_q_prompt register should be read last, because this resets the chx_new_accum_data bit. the chx_missed_accum bits in the accum_status_b register indicate that new accumulated data has been missed. these can only be cleared by a write to chx_accum_reset or by deactivating the channel. search on other code phases when it is desired to correlate on the next code phase, such as one whole chip later, the code_slew has to be programmed with a value of 2 (the units are half code chips). the slew will occur on the next dump. the effect of code_slew is relative to the current code phase. to repeat a code_slew, the register needs to be written to again even if the same size slew is required. once the signal has been detected (correlation threshold exceeded), the code and carrier tracking loops can be closed. the tracking loop parameters must be tailored in the software to suit the application. data bit synchronisation the data bit synchronisation algorithm should find the data bit transition instant. the processor calculates the present one millisecond epoch and programs this value into the 1ms_epoch counter. ideally, epoch counter accesses should occur following the reading of the accumulation register at each dump. alternatively, the epoch counters can be left freeCrunning and the offset can be added by the software each time it reads the epoch registers. note that if the integration is performed across bit boundaries, the integration result can be very small. reading the measurement data at each tic, the measurement data is latched in the measurement data registers (chx_epoch, chx_code_phase, chx_carrier_dco_phase, chx_carrier_cycle_high, chx_carrier_cycle_low, chx_code_dco_phase ). the accum_status_b or meas_status_a register must be polled at a rate greater than the tic rate (to see if a tic has occurred), otherwise measurement data will be lost. the accum_int or meas_int events can be used
23 GP2021 to instigate this operation. the reading of measurement data can be either interrupt driven or polled. for the interrupt driven method the microprocessor reads the accum_status_b or meas_status_a register after each meas_int, and if the tic bit is set, subsequently reads the measurement data. for the polled method the accum_status_a register is always read following every accum_int. in addition the accum_status_b register is read on each accum_int to ensure no accumulated data has been missed and to check the tic bit (along with several other status bits). the software tests the tic bit to determine if new measurement data is available to be read. preset mode each channel can be programmed into preset mode by writing a high into the preset/updateb bit of the chx_satcntl register. when a tic occurs, the satellite code, epoch value and slew numbers are loaded, and a new phase programmed into the code dco regardless of its previous value. prior to the tic the channel operates with its previous settings. preset mode has no effect on the carrier dco and carrier cycle counter. if preset mode is initiated, it should be allowed to operate to completion. the required sequence of operations is as follows: (i) write into chx_satcntl to select the preset mode, together with the appropriate new settings. ii) load the code and carrier dco increment values. note: these will take effect immediately thereby influencing the current measurements. iii) load the following registers: chx_code_dco_phase, chx_code_slew and chx_epoch_count_load. it is important that the chx_epoch_count_load occurs last, because it enables the preset operation on the next tic. interrupts there are 2 interrupt sources: accum_int and meas_int. their sense is dependant upon the selected microprocessor interface mode. the default accum_int period is 505.05 m s. however, it can be reconfigured via the prog_accum_int register or by changing the interrupt_period or front_end_mode bits in the system_setup register. the default meas_int period is 50ms. however, this can be reconfigured via the prog_tic_high and prog_tic_low registers. signal path delay introduced by hardware signal processing when it is desired to generate an accurate time reference from gps signals or to timeCstamp position fixes the delays in the receiver must be allowed for. the signal path delay has two components, an analogue path delay which varies with tem- perature and component tolerances; and a digital path delay which is constant if oscillator drift variations are neglected. the digital delay is easier to estimate and is made up of the following: in real_input mode: (i) the time from the sampling edge of the sign and mag bits in the front end (sampclk) to the reCsampling in the sample latch (175 ns less the propagation delay of sampclk to the frontCend). (ii) plus the time for the correlation in the correlator on these same sign and mag bits (125 ns). (iii) plus the delay in the accumulator to latch the sampled data (175 ns ). (iv) less the time between the correlation and the tic clock phase which is before the accumulator latch phase (75 ns), giving a total of 400 ns less the sampclk delay. in complex_input mode: (i) the time for the correlation in the correlator on the sign and mag bits after sampling (114 ns). (ii) plus the delay in the accumulator to latch the sampled data (171 ns ). (iii) less the time between the correlation and the tic clock phase which is before the accumulator latch phase (86 ns), giving a total of 199 ns. the analog delay through the radio receiver is set by such parameters as group delay in filters, which for the bandwidths used for c/a code will be in the region of 1 to 2 ms and so swamps the digital delay, but this can be measured and corrected for. integrated carrier phase measurement the correlator tracking channel hardware allows meas- urement of integrated carrier phase through the chx_carrier_cycle_high and _low and the chx_carrier_dco_phase registers, which are part of the measurement data sampled at every tic. the chx_carrier_cycle_high and _low registers contain the (20 bit) number of positiveCgoing zero crossings of the carrier dco; this will be one more than the number of full cycles elapsed ( 4 bits are in _high and 16 in _low register). the chx_carrier_dco_phase register contains the cy- cle fraction or phase, with 10 bit resolution to give 2 p / 1024 radian increments. to get the integrated carrier phase over several tic periods all that is needed is to read the chx_carrier_cycle_high and _low registers at every tic and sum the readings. this gives a number 1 higher than the number of complete carrier cycles, when a carrier cycle is measured from one positiveCgoing zero crossing to the next. to this number, the fractional carrier cycle at the end has to be added, and the fractional carrier cycle at the beginning has to be subtracted. both numbers are read from the chx_carr_dco_phase register. the total phase change can be calculated as follows : integrated carrier phase = 2 p * ? numbers in carrier cycle counter + final carrier dco phase Cinitial carrier dco phase fig. 22 shows how this equation is derived.
24 GP2021 this integrated carrier phase may be related to the deltaCrange, (the change in distance to each satellite). when used with the orbital parameters of the satellites, the deltaC ranges give a measure of the receivers movement between fixes, which is independent of those fixes and so can be used to smooth them. it can also give a velocity directly. the deltaC ranges will be noisy and most of the value is due to satellite movement so the determination of velocity must use data from adequately separated tics. for position smoothing all deltaC ranges may be included in the input to the navigation filter, as that filter will perform a running average of the deltaCranges as well as the ranges. timemark generation the GP2021 is capable of generating an accurate timemark timing output on one of the discrete outputs if required. timemark is intended to be a utc aligned timing output with an accurate 1 second period and a pulse width of 1ms. the timemark output is always derived from a rising edge on tic, and for utc aligned operation the tic counter must be brought into phase with utc. this is done by modifying the division ratio of the tic counter for a single tic period, by increasing or reducing the division ratio, thus slewing the phase of tic. since the tic counter is incremented every 175ns which is not an exact subCmultiple of 1 second it is also necessary to continually monitor the relationship between tic and utc to keep tic in phase with utc. once tic is in phase with utc, the timemark output can be derived from tic using one of 2 methods both of which involves writing to timemark_control: (1) the GP2021 can be armed to produce a timemark output at the next tic only, or (2) it can be programmed to give a timemark output every n tics starting at the next tic. a separate counter resets the timemark output giving a 1ms pulse width. the tic counter can be programmed with an accuracy of 175ns in real_input mode or 171.4ns in complex_input mode. this determines the accuracy of the timemark output. if the tic is continually synchronised to keep the rising edge as close as possible to utc, the internal timemark will be within 100ns (4/7 x 175ns) of utc in real_input mode or 85.7ns (3/6 x 171.4ns) of utc in complex_input mode. in addition, there may be a delay of up to 50ns in getting the timemark output off chip, giving a maximum error of 150ns (real_input) or 135.7ns (complex_input) between timemark and utc. it should be noted that due to the need to reCsynchronise tic, a jitter of up to 175ns may be present on timemark, along with any jitter and drift present on the input clock. the pulse width of timemark (in seconds) is either (5714 + 2/7) * (7/ master clock frequency) for real_input mode giving 1.0000000ms (assuming an accurate 40mhz master clock input) or (5833 + 1/6) * (6 / master clock frequency) for complex_input mode giving 0.9999714ms (assuming an accurate 35mhz master clock input). ph ph ph kk cycles cycles tic tic tic 11 1 0 0 22 2 y 2 y 1 1. reading at tic 0 : chx_carr_dco_phase 0 = ph 0 2. reading at tic 1 : chx_carr_dco_phase 1 = ph 1 chx_carr_cycle 1 = k 1 + 1 3. reading at tic 2 : chx_carr_dco_phase 2 = ph 2 chx_carr_cycle 2 = k 2 + 1 d y1 = 2 p * k 1 + (2 p ?ph 0 ) + ph 1 = 2 p (k 1 + 1) ?ph 0 + ph 1 = 2 p * (chx_carr_cycle 1 ?chx_carr_dco_phase 0 /1024 + chx_carr_dco_phase 1 /1024) d y = 2 p *( last i1 chx_carr_cycle i chx_carr_dco_phase 0 1024 chx_carr_dco_phase last 1024) note: the carrier cycle counter value is stored at every tic and the counter is reset fig.22 integrated carrier phase
25 GP2021 detailed description of registers GP2021 register map the register map of the GP2021 is shown below. the addresses are complete, and it should be noted that all the register addresses are wordCaligned, i.e. a0 and a1 are not used. adjacent register addresses thus increment by 4, in arm system mode. however, in standard interface mode, the GP2021 address lines a<9:2> could be connected to the processor address lines a<7:0>. note that in this mode pins a0 and a1 are allocated other functions. address (hex) address (hex) registers register arm system mode standard block interface mode a<22:20> a,9:0> a<9:2> correlator cntl 2 000 to 01c 00 to 07 cho control cntl 2 020 to 03c 08 to of ch1 control cntl 2 040 to 05c 10 to 17 ch2 control cntl 2 060 to 07c 18 to 1f ch3 control cntl 2 080 to 09c 20 to 27 ch4 control cntl 2 0a0 to 0bc 28 to 2f ch5 control cntl 2 0c0 to 0dc 30 to 37 ch6 control cntl 2 0e0 to 0fc 38 to 3f ch7 control cntl 2 100 to 11c 40 to 47 ch8 control cntl 2 120 to 13c 48 to 4f ch9 control cntl 2 140 to 15c 50 to 57 ch10 control cntl 2 160 to 05c 58 to 5f ch11 control cntl 2 180 to 19c 60 to 67 multi control 2 1a4 69 x_dco_incr_high 2 1ac 6b prog_accum_int 2 1b4 6d prog_tic_high 2 1bc 6f prog_tic_low cntl 2 1c0 to 1dc 70 to 77 all control 2 1ec 7b timemark_control 2 1fo 7c test_control 2 1f4 7d multi_channel_select 2 1f8 7e system_setup 2 1fc 7f reset_control 2 200 to 20c 80 to 83 status registers accum 2 210 to 21c 84 to 83 cho accumulate accum 2 220 to 22c 88 to 8b ch1 accumulate accum 2 230 to 23c 8c to 8f ch2 accumulate accum 2 240 to 24c 90 to 93 ch3 accumulate accum 2 260 to 26c 98 to 9b ch5 accumulate accum 2 270 to 27c 9c to 9f ch6 accumulate accum 2 280 to 28c a0 to a3 ch7 accumulate accum 2 290 to 29c a4 to a7 ch8 accumulate accum 2 2a0 to 2ac a8 to ab ch9 accumulate accum 2 2b0 to 2bc ac to af ch10 accumulate accum 2 2c0 to 2bc b0 to b3 ch11 accumulate accum 2 2d0 to 2dc b4 to b7 multi accumulate accum 2 2e0 to 2ec b8 to bb all accumulate
26 GP2021 correlator registers addresses for the correlator registers may be calculated from a base address with an increment for a particular register. the base addresses for the cntl and accum register blocks for each channel in the correlator are shown in the GP2021 register map, the increments being given below: eg. ch3_code_dco_incr_low = 060h + 018h = 078h address (hex) address (hex) registers register arm system mode standard block interface mode a<22:20> a,9:0> a<9:2> real -time clock 3 000 c0 rtc_ls 3 004 c1 rtc_2nd 3 008 c2 rtc_ms 3 00c c3 clock_reset 3 010 c4 watchdog_reset duart 3 040 d0 tx_data_a, rx_data_a 3 044 d1 tx_data_a, rx_data_b 3 048 d2 config_a, status_a 3 04c d3 config_a, status_b 3 050 d4 ch10 control 3 054 d5 ch11 control 3 058 d6 multi control 3 05c d7 x_dco_incr_high system control 3 080 e0 wait_state 3 084 e1 system_config 3 088 e2 not used 3 08c e3 system_error_status 3 090 e4 data_retent general control 3 0c0 f0 io_config 3 0c4 f1 test_config 3 0c8 f2 data bus test table 8: GP2021 register map
27 GP2021 note: the registers labelled * (the code_phase_counter and carrier_cycle_control) can only be written to if test mode has been selected by setting bit 3 of the test control register to high. in both the accum and cntl sections there are some addresses labelled all or multi in place of chx. writing to these addresses will write to all channels or to a selection set by multi_channel_select in one operation and so may be used to initialise the system quickly or to load the next search settings with little bus use. this is a write only function and the corresponding chx read functions are not available at addresses labelled all or multi. it can be seen that the addresses in cntl are used to control the device in write mode but give the measurement data when in read mode. apart from the code and carrier dco increment values all data transfers are only 16 bit wide. writes to the code and carrier dcos are 32 bit data transfers where the _high word should be written first and will be retained in the 16 to 32 bit interface until the _low word is written, which must occur as the next write to the chip. all 32 bits will then be transferred into the dco increment register. data is written to an input buffer in the 16 to 32 bit interface and will be transferred to its destination register during the next full cycle of the 7 (or 6) phase clock. write cycles should therefore have a period of at least 300 ns. the x_dco_incr_high may be used to write the high bits of the increment number to any or all dcos as an alternative to using the chx_code carrier_dco_incrC _high addresses. by using this address, there is no need to wait 300ns before writing the _low part. for further information refer to general interface timing in microprocessor interface section. the bit assignments for the correlator registers are given below, but two writeConly registers do not have any data bits, these are: (1) a write to the chx_accum_reset register (irrespective of what data is written) will reset the accum_status_a, accum_status_b, and accum_status_c registers for that channel. (2) a write to the status register (irrespective of what data is written) will latch the state of the various status flags into accum_status_a, accum_status_b, accum_status_c registers for all channels. this allows a polling based rather than interrupt driven tracking scheme. the registers are listed in alphabetical order and not in address order to allow easy reference to each section. unless otherwise stated the lsb is bit 0 and the msb is bit 15 or as far up the register as there is data. note that most registers do not have both read and write functions, and many addresses are shared between readConly and writeConly registers having different functions. address (hex) write function read function arm system standard mode interface mode 200 80 status accum_status_c 204 81 not used meas_status_a 208 82 not used accum_status_a 20c 83 not used accum_status_b address (hex) write function read function arm mode standard system interface mode cntl + 00 cntl + 0 satcntl code_slew + 04 + 1 code phase counter* code_phase + 08 + 2 carrier_cycle_counter* carrier_cycle_low + 0c + 3 carrier_dco_incr_high carrier_dco_phase + 10 + 4 carrier_dco_incr_low epoch (latched0 + 14 + 5 code_dco_incr_high code_dco_phase + 18 + 6 code_dco_incr_low carrier_cycle_high + 1c + 7 epoch_count_load epoch_check (not latched) accum + 00 accum + 0 code_slew_counter i_track + 04 + 1 accum_reset q_track + 08 + 2 not used i_prompt + 0c + 3 code_dco_preset_phase q_prompt tracking channel registers
28 GP2021 accum_status_a (read address) bit bit name 15 accum_int 14 not used Clow 13 not used Clow 12 not used Clow 11 ch11_new_accum_data 10 ch10_new_accum_data 9 ch9_new_accum_data 8 ch8_new_accum_data 7 ch7_new_accum_data 6 ch6_new_accum_data 5 ch5_new_accum_data 4 ch4_new_accum_data 3 ch3_new_accum_data 2 ch2_new_accum_data 1 ch1_new_accum_data 0 ch0_new_accum_data accum_status_a is a register containing the state of twelve status bits sampled and latched on the active edge of every accum_int. they can also be sampled and latched on request, by performing a write operation to status. (this is safe only if the interrupts are stopped, by setting interrupt_enable bit to low in the system_setup register.) the microprocessor must respond to each accum_int and read the channel registers before the next dump is due in that channel. the accum_int bit is set high at every accum_int and is reset by reading the accum_status_a register. this status bit is reset by a hardware master reset but not by a software reset (mrb). the chx_new_accum_data status bit indicates that a dump has occurred in that channel, and that new accumulated data is available to be read. each bit is cleared by the trailing edge of a read of the associated chx_q_prompt register or by a write to chx_accum_reset. note that the channel specific bits of this register will not show their new value until after an active edge of accum_int or a write to the status register. disabling a channel will however, clear the bit immediately. accum_status_b (read address) bit bit name 15 discip_glitch 14 discip 13 tic 12 meas_int 11 ch11_missed_accum 10 ch10_missed_accum 9 ch9_missed_accum 8 ch8_missed_accum 7 ch7_missed_accum 6 ch6_missed_accum 5 ch5_missed_accum 4 ch4_missed_accum 3 ch3_missed_accum 2 ch2_missed_accum 1 ch1_missed_accum 0 ch0_missed_accum the lower 12 bits of accum_status_b bits are sampled and latched on the active edge of every accum_int signal. they can be sampled and latched on request by performing a write operation to status (as with accum_status_a). the discip_glitch bit will be set high if a glitch to low has occurred on the discip pin since the last read of this register. it is cleared by reading this accum_status_b register. this bit is reset by a hardware master reset (resetb at low) but not by a software reset. the minimum reliably detectable glitch width is 25ns. the discip bit indicates the level on the discip input pin at the time this read occurs and may be used to interface a hardware condition (such as a ready flag from a uart or the pll lock signal from a frontCend) to the microprocessor without using an interrupt. this bit is not reset by a hardware master reset nor by an mrb. the tic bit is set high at every tic and is cleared by reading this accum_status_b register. its purpose is to tell the microprocessor that new measurement data is available. it is reset by a hardware master reset (resetb at low) but not by an mrb in reset_control. provided that interrupts are enabled, the meas_int bit is set high at each tic and 50 ms before each tic ( if the tic period is greater then 50 ms), and is cleared by reading this register. this bit can be used as a flag to the microprocessor, to time software module swapping. it is reset by a hardware master reset (resetb at low), but not by a software reset. chx_missed_accum status bit indicates (when high) that there has been missed accumulated data due to a new dump in chx before the previous data has been read. this bit is latched until the associated chx_accum_reset is written to. if any data is missed due to the reading process being too slow this must be allowed for in the software, such as by checking the navigation message data bit transitions independently of the sets of accumulated data reads. if too much data is lost the system signal to noise ratio will be degraded. the primary purpose of these bits is as a check on how well the tracking routines are working C once the whole design is complete these bits should not become set. note that the channel specific bits of this register will not show their new value until after an active edge of accum_int or a write to the status register. disabling a channel will however, clear the bit immediately. accum_status_c (read address) bit bit name 15 not used C low 14 not used C low 13 not used C low 12 not used C low 11 ch11_early_lateb 10 ch10_early_lateb 9 ch9_early_lateb 8 ch8_early_lateb 7 ch7_early_lateb 6 ch6_early_lateb 5 ch5_early_lateb 4 ch4_early_lateb 3 ch3_early_lateb 2 ch2_early_lateb 1 ch1_early_lateb 0 ch0_early_lateb
29 GP2021 chx_accum_reset (write address) bits 15 to 0: not used. these are writeConly locations provided to allow resetting of the status bits accum_status_a, accum_status_b, and accum_status_c associated with a given channel or all channels. when these locations are written to, the data is irrelevant. chx_carrier_cycle_counter, multi_carrier_cycle_counter, all _carrier_cycle_counter (write address) a write to these registers only has effect when in test mode (bit 3 of test_control set high). the value on the bus is loaded into the lower 16 bits of the chx_carrier_cycle_counter along with zeros into the upper 4 bits. chx_carrier_cycle_high, chx_carrier_cycle_low (read address) _high bits 15 to 4 : not used C low when read. _high bits 3 to 0: carrier cycle count bits 19 to 16. _low bits 15 to 0: carrier cycle count bits 15 to 0. the correlator tracking channel hardware allows for measurement of integrated carrier phase through the chx_carrier_cycle_high and _low and the chx_carrier_dco_phase registers, which are part of the measurement data sampled at every tic. the chx_carrier_cycle_high and _low registers contain the 20 bit number of positive going zero crossings of the carrier dco (4 bits are in _high and 16 in _low). the cycle fraction can be read from the chx_carrier_dco_phase register. in the chx_carrier_cycle counter, a tic generates two consecutive actions. first it latches the 4 more significant bits of the cycle counter into chx_carrier_cycle_high and the 16 less significant bits into chx_carrier_cycle_low. then it resets the cycle counter. after each tic, every time the carrier dco accumulator generates an overflow as a result of a carrier cycle being completed, the cycle counter increments by one. in real_input mode the nominal carrier dco frequency with no doppler and no oscillator drift compensation is 1405396825 mhz, so in 100 ms, there will be about 140540 cycles. in almost all applications the number of carrier dco cycles does not vary much from one tic interval to another so it is possible to predict the most significant bits of the value, and then only read the chx_carrier_cycle_low register. chx_carrier_cycle_high and _low contents are not protected by an overwrite protection mechanism and so must be read before the next tic. for further information on the carrier cycle counter refer to detailed operation of GP2021.* * refer to page 9. chx_carrier_dco_incr_high, x_dco_incr_high, multi_carrier_dco_incr_high, all_carrier_dco_incr_high, chx_carrier_dco_incr_low, multi_carrier_dco_incr_low, all_carrier_dco_incr_low (write address) _incr_high bits 15 to 10: not used in this operation. _incr_high bits 9 to 0 : more significant bits (25 to 16) of the carrier dco phase increment when used before a write to _carrier_dco_incr_low. _incr_low bits 15 to 0 : less significant bits (15 to 0) of the carrier dco phase increment. the contents of registers _incr_high and_incr_low are combined to form the 26 bits of the chx_carrier_dco_incr register, the carrier dco phase increment number. in order to write successfully, the top 10 bits must be written first, to any of the _high addresses. they will be stored in a buffer and only be transferred into the increment register of the dco together with the _low word. a 26 bit increment number is adequate for a 27 bit accumulator dco, as the increment to the msb is always zero. the lsb of the incr register represents a step given by: min step frequency = (40mhz/7)/2 27 (in real_input mode) = 42.57475mhz min step frequency = (35mhz/6)/2 27 (in complex_input mode) = 43.46172mhz the output frequency = chx_carrier_dco_incr * min step frequency. with a gp2015/gp2010 style front end, the nominal value of the if is 1.405396826 mhz before allowing for doppler shift or crystal error. writing 01f7b1b9h into the chx_carrier_dco_incr register will generate a local oscillator frequency of 1.405396845 mhz. chx_carrier_dco_phase (read address) bits 15 to 10: not used C low when read. bits 9 to 0: more significant bits (26 to 17) of chx_carrier_dco_phase as sampled at the last tic. the weight of the least significant bit is 2 p / 1024 radians of a carrier dco cycle. these bits form an unsigned integer valid from 0 to 1023. chx_carrier_dco_phase provides accum_status_c bits are sampled and latched on the active edge of every accum_int signal, or they can be sampled and latched on request by performing a write operation to status (as with accum_status_a). chx_early_lateb status bit indicates the code type for the accumulated data on the tracking arm of channel chx when that channel is in dithering mode. a high indicates an early code and a low indicates a late code. each individual bit is determined on the dump that sets chx_new_accum_data to high for that channel. in other modes the bit is of no use. note that the channel specific bits of this register will not show their new value until after an active edge of accum_int or a write to the status register. disabling a channel will however, clear the bit immediately.
30 GP2021 chx_code_dco_incr_high, x_dco_incr_high, multi_code_dco_incr_high, all_code_dco_incr_high, chx_code_dco_incr_low, multi_code_dco_incr_low, all_code_dco_incr_low ( write address) _incr_high bits 15 to 9: not used in this operation. _incr_high bits 8 to 0: more significant bits (24 to 16) of the code dco phase increment when used before a code_dco_incr_low. _incr_low bits 15 to 0: less significant bits (15 to 0) of the code dco phase increment. the contents of registers _incr_high and _incr_low are combined to form the 25 bits of the chx_code_dco_incr register, the code dco phase increment number. in order to write successfully, the top 9 bits must be written first, to any of the _high addresses. they will be stored in a buffer and only be transferred into the increment register of the dco together with the _low word. a 25 bit increment number is adequate for a 26 bit accumulator dco as the increment to the msb is always zero. the lsb of the incr register represents a step given by: min step frequency = (40mhz/7)/2 26 (in real_input mode) = 85.14949mhz min step frequency = (35mhz/6)/2 26 (in complex_input mode) = 86.92344mhz the output frequency = chx_code_dco_incr * min step frequency. note: the code dco drives the code generator to give half chip time steps and so must be programmed to twice the required chip rate. this means that the chip rate resolution is 4257475mhz in real_input mode or 43.46172mhz in complex_mode. the nominal frequency is 1.023000000 mhz before allowing for doppler shift or crystal error. writing 016ea4a8h into the chx_code_dco_incr register will generate a chip rate of 1.022999968 mhz in real_input mode. in complex_mode, 01672922h will generate a chip rate of 1.022999970 mhz. chx_code_dco_phase ( read address) bits 15 to 10: not used, (low when read). bits 9 to 0: chx_code_dco_phase: contains the ten more significant bits (25 to 16) of the code dco phase accumulator sampled at a tic event. it is an unsigned integer valid from 0 to 1023. the weight of the least significant bit is 2 p /1024 radians, 2 p being half of a code chip, so the pseudorange resolution is 1/2048 of a chip, (equivalent to 015 metre or 05ns). the chx_code_dco_phase content is not protected by any overwrite protection mechanism. chx_code_dco_preset_phase, multi_code_dco_preset_phase, all_code_dco_preset_phase ( write address) bits 15 to 8: not used. bits 7 to 0: more significant bits (25 to 18) of the code dco phase which is to be loaded at the next tic event in preset mode. in preset mode, the 8 bits of the chx_code_dco_preset_phase register, with zeros filling the lower bits, are transferred to the code dco accumulator on the next tic. the previous accumulator phase is totally overwritten. the preset_phase register is a writeConly register and it can be written to at any time in preset mode or in update mode, but only has effect when preset mode is entered. the weight of the least significant bit of preset phase is 2 / 256 radians of a half chip cycle. in update mode this register has no use other than as preparation for preset mode. refer to detailed operation of GP2021 for further information on preset mode. * * refer to page 9. chx_code_phase (read address) chx_code_phase_counter, multi_code_phase_counter, all_code_phase_counter (write address) bits 15 to 11: not used, low when read. bits 10 to 0: chx_code_phase (read) C this is the state of the code phase counter, (an 11Cbit binary up counter clocked by the code generator clock), stored on tic. the phase is expressed as a number of half code chips and ranges from 0 to 2046 half chips. a reading of 2046 is very rare and can only occur if the tic captures the code phase just after the counter reaches 2046 and before it is reset by a dump from the c/a code generator. dump also increments the epoch counter, so the meaning of a phase value of 2046 + the previous epoch value is the same as a phase value of 0 + the incremented epoch value, and either is valid. if a tic occurs during a code slew the reading will be 0, and that channels measurement data is of no use. bits 10 to 0: (write) loads the 11 bits of the chx_code_phase_counter. a write to these registers is only possible in test mode, enabled by setting the tm_test (bit of test_control) to high. chx_code_slew (read address) chx_code_slew_counter, multi_code_slew_counter, all_code_slew_counter (write address) bits 15 to 11: not used. bits 10 to 0 : an unsigned integer ranging from 0 to 2047 representing the number of code half chips to be slewed immediately after the next dump if in update mode or after the next tic, if in preset mode. since there are only 2046 sub-cycle phase measurement information and so complements the information given by chx_carrier_cycle_high and _low. the register value is latched on each tic and is not protected by any overwrite protection mechanism.
31 GP2021 chx_epoch_check ( read address) bits 15 to 14: not used. bits 13 to 8 : instantaneous value of chx_20ms_epoch. bits 7 to 5 : not used. bits 4 to 0 : instantaneous value of chx_1ms_epoch. reading this address gives the instantaneous value of the chx_1ms_epoch and the chx_20ms_epoch counters. it can be used to verify if the epoch counters have been properly initialised by the software. its value is not latched and is incremented on each dump. to ensure the correct result, this register should be read only when there is no possibility of getting a dump during the read cycle, by synchronising the read to new_accum_data. the ranges of these values are the same as those seen in the chx_epoch register. chx_epoch (read address) bits 15, 14, 7, 6 and 5: not used. read gives low. bits 13 to 8: chx_20ms_epoch: the 20 ms epoch counter value that was sampled at the last tic event, with a valid range from 0 to 49. bits 4 to 0: chx_1ms_epoch: the 1 ms epoch counter value that was sampled at the last tic event, with a valid range from 0 to 19. chx_epoch_count_load multi_epoch_count_load all_epoch_count_load (write address) bits 15, 14, 7, 6, and 5: not used. bits 13 to 8: chx_20ms_epoch: the value to be loaded into the 20 millisecond epoch counter, with a valid range from 0 to 49. bits 4 to 0: chx_1ms_epoch: the value to be loaded into the 1 millisecond epoch counter, with a valid range from 0 to 19. this operation is affected by the current channel mode, (preset or update). in update mode, the data written into these registers is immediately transferred to the 1 ms and 20 ms epoch counters. in preset mode however, the data is transferred only after the next tic. it is important to load the chx_epoch register last in the preset mode loading sequence because the trailing edge of a write to this register enables the whole preset operation on the next tic. refer to detailed operation of the GP2021 for more details of the preset mode. * * refer to page 23 half chips in a gps c/a code, a programmed value of 2047 is equivalent to a programmed value of 1, but the next dump event will take place 1 ms later. in preset mode, the slew timing is set only by tic, which will also reset the code generator, (no dump is needed). a nonCzero slew must always be programmed when using preset mode. the chx_code_slew register can be written to at any time. if two accesses have taken place before a dump in update mode or before a tic when in preset mode, the latest value will be used at the next slew operation. during the time a slew process is being executed, any further write access to the chx_code_slew register will be stored until the following dump and then cause the transfer of this new value into the counter. this situation may be avoided by synchronising the access with the associated chx_new_accum_data status bit. if a channel is inactive, a nonCzero slew value should be written into chx_code_slew before the channel is released. this write will be acted on immediately the reset is released. if a tic occurs during or soon after a slew the channel will not be locked to the satellite, so the measurement data for that channel will not be of use. the ability to read the slew counter is included only for testing hardware or software and has no other use. it will only give a nonCzero result if the read occurs during the actual slew operation. an example of a slewing event is shown in fig.23. t1: load 5 into chx_code_slew register = 2.5 chips delay 1023 chips 1025.5 chips dump dump dump time t1 c/a code chip no.: 1021 1022 1023 1 1 1 1 2 3 fig.23 slew timing in update mode
32 GP2021 gps prn bit setting gps prn bit setting signal no 9 to 0 signal no 9 to 0 1 3f6h 24 338h 2 3ech 25 27oh 3 3d8h 26 oedh 4 3boh 27 1coh 5 04bh 28 38oh 6 096h 29 22bh 7 2cbh 30 056h 8 196h 31 oach 9 32ch 32 158h 10 3bah 33 2boh 11 374h 34* 058h 12 1doh 35 18bh 13 3aoh 36 316h 14 340h 37* 058h 15 280h 201 gic 2c4h 16 100h1 202 gic 10ah 17 113h 205 gic 3e3h 18 226h 206 gic of8h 19 04ch 207 gic 25fh 20 098h 208 gic 1e7h 21 130h 209 gic 2b5h 22 260h 211 gic 10eh 23 267h chx_i_track, chx_q_track, chx_i_prompt, chx_q_prompt ( read address) bits 15 to 0: accumulated data registers, which are used on each dump to store the 16Cbit integrateCandCdump accumulator results. the values contained in the registers are 2s complement values with the valid range of the data from C2 15 to +(2 15 C1). these registers are readConly registers which can be read at any time. their content is not protected by any overwrite protection mechanism, so the set of four registers must be read soon after a accum_int to be sure that newer data will not cause an overwrite part way through the set. the chx_i_prompt and chx_q_prompt contain the accumulated data from the prompt arm. the chx_i_track and chx_q_track contain the accumulated data from the tracking arm. to track satellites correctly, only data read with the chx_new_accum_data bit set high should be used. an overflow or underflow condition cannot be reached. chx_satcntl, multi_ satcntl, all_satcntl (write address) bit bit name 15 gps_nglon 14 to 13 track_sel 12 preset/updateb 11 code_off/onb 10 sourcesel 9 to 0 g2_load (9 to 0) chx_satcntl is a writeConly register that can be written into at any time. any modification to the content is effective at the next dump in update mode or at the next tic in preset mode for all bits, apart from preset updateb,which defines whether a channel is in preset or update mode. it is important to program this register first when starting the initialisation of a preset sequence to get the channel into preset mode, or the other write operations will act too soon. g2_load (9 to 0), bits 9 to 0: c/a code selection function: the chx_satcntl register programs the code generator by setting the g2 register to the appropriate starting pattern to generate the required gps or inmarsatCgic codes. the g2_load register may be programmed at any time but the value is only used when the code sequence restarts, at the following dump in update mode, or at the following tic in preset mode. the pattern to load is the register state for the time of the second code chip. the following table shows the values required to select one of the 37 gps or the 8 inmarsatCgic possible prn (pseudo random noise) patterns. in update mode, the c/a code generated by the code generator will be changed at the dump following the write to chx_satcntl and at this dump the accumulated data will be valid for the previous code selection. later dumps will be valid for the new code. if all zeros are loaded into the g2 register it will not clock out, and the g1 generator code will be seen on the output. this is an illegal state which is only of use for chip testing. prn sequences 201 to 211 are selected for inmarsat gic (gps integrity channel) use.due to the initialisation of the earlyCpromptClate shift register, all codes will always start with a 1 for the first bit of the sequence after a code change or a code slew. subsequent cycles of the prn sequence will be correct for the chosen satellite. sourcesel, bit 10: selects which input source to be used by the channel when in real_input mode. low selects sign0 and mag0, high selects sign1 and mag1. code_off/onb, bit 11: when low, the code is output normally, but when high, the prompt, early and late codes are held high (code mixer outputs exactly follow inputs) and the earlyCminusClate code is held low. this is intended for test purposes only. preset/updateb, bit 12: when high sets the channel into preset mode, or when low, sets the channel into update mode. this bit is cleared to low after the preset function has been done, that is after the first tic following the loading of the epoch counters. track_sel (1 and 0), bits 14 and 13: select the appropriate code to be produced by the tracking arm output of the code generator as follows: table 9 : g2 load settings required for satellite selection. *c/a codes 34 and 37 are equivalent. notes: prn sequences 33 to 37 are reserved for nonCsatellite uses (e.g. ground transmitters).
33 GP2021 when the dithering code has been selected, the tracking arm will use the early code for 20 periods of the gold code, the late code for the next 20 periods and then this process of alternating between early and late code will be repeated indefinitely. the tracking arm will toggle between early or late codes on every increment of a 20ms epoch count. its state can be determined by reading the accum_status_c register. the output code is a sequence of +1s and C1s for all code types except earlyCminusClate where the result can also be a 0. in earlyCminusClate mode the values are not the +2,0, C2 that results from the calculation (+1 or C1) C (+1 or C1), but are halved to +1, 0, C1. this must be considered when choosing thresholds in the software as the correlation results will be exactly half of the values otherwise expected. gps nglon, bit 15: setting this bit to low changes the c/a code generator mode to glonass mode, to generate the fixed 511 bit sequence used by all glonass satellites. after a master reset, gps mode is selected, but with all zeros in the g2 generator, the g1 code is seen at the output of the c/a code generator. meas_status_a ( read address) bit bit name 15 to 14 not used 13 tic 12 meas_int 11 ch11_missed_meas_data 10 ch10_missed_meas_data 9 ch9_missed_meas_data 8 ch8_missed_meas_data 7 ch7_missed_meas_data 6 ch6_missed_meas_data 5 ch5_missed_meas_data 4 ch4_missed_meas_data 3 ch3_missed_meas_data 2 ch2_missed_meas_data 1 ch1_missed_meas_data 0 ch0_missed_meas_data when a chx_missed_meas_data status bit is high, it indicates that one or more sets of measurement data have been missed since the last read from this register. it is set high by a read from the code phase counter of the same channel, when the previous value in the code phase counter has not been read, and is reset by a read from the meas_status_a register or by disabling the channel. if this register is always read after the code phase counter, it indicates whether measurement data has been missed before the last read of the code phase counter. all chx_missed_meas_data bits are set low by a hardware or software reset. the meas_int bit is set high at each tic and 50 ms before each tic ( if tic period is greater then 50 ms), and is cleared by reading this register. the purpose of the bit, is a flag to the microprocessor, to time software module swapping. this bit is reset by a hardware master reset (resetb at low) but not by a software reset. the tic bit is set high at every tic and is cleared by reading this register. the purpose of the bit is to tell the microprocessor that new measurement data is available. this bit is reset by a hardware master reset (resetb at low) but not by an mrb in reset_control. multi_channel_select ( write address) bit bit name 15 to 12 not used 11 ch11_select 10 ch10_select 9 ch9_select 8 ch8_select 7 ch7_select 6 ch6_select 5 ch5_select 4 ch4_select 3 ch3_select 2 ch2_select 1 ch1_select 0 ch0_select chx_select, when set high, enables the multiC channel write operations on chx. this may be used to set several channels to mostly the same conditions. for a parallel search for one satellite, operations such as setting each carrier dco to the same frequency; or during that search, to adjust all selected channels by the same value, (such as a code slew to shift the code phases together to a new search area) could use this feature. all chx_select are set low by a (hardware or software) master reset. prog_accum_int ( write address) bits 15 to 13: not used. bits 12 to 0: accum_int division ratio. the prog_accum_int register location operates in conjunction with the interrupt_period bit of the system_setup register to set the period of the accum_int output. accum_int is generated by a 13 bit binary down counter which counts down to zero, producing an accum_int output. it then loads to a preset value stored in its preset register and starts to count down again. if the preset value is p, the count sequence is p, pC1, pC2, ..., 1, 0, p, pC 1. hence, the counter divides by p+1, producing an output with a period of (p+1) * clock period. since the accum_int counter is clocked by the multiCphase clock, the clock rate is either 7 * clock period (nominally 40mhz, i.e. 25ns) for real_input mode, or 6 * clock period (nominally 35mhz, i.e. 14 13 code select 0 0 early code 0 1 late code 1 0 dithering code (alternating early and late) 1 1 earlyCminusClate code table 10: track_sel bit settings for tracking arm code selection.
34 GP2021 28.571429ns) for complex_input mode. the value stored in the preset register can be modified in one of two ways: either by toggling the interrupt_period or front_end_mode bits of the system_setup register, or by writing to the prog_accum_int location. either of these actions will overwrite the previous contents of the preset value and either one or both methods may be used. if the interrupt counter detects an edge on either the interrupt_period or front_end_mode bits it will load one of four values in to the preset register, depending upon the new value of both interrupt_period and front_end_mode. these four presets are as shown in table 12. the value for interrupt_period = low and front_end_mode = low is also that loaded on a master reset. alternatively the accum_int counter may be loaded by writing direct to the prog_accum_int location. in this case the new accum_int period is as follows: accum_int period = (prog_accum_int + 1) * 7 (40mhz) (real input mode) accum_int period = (prog_accum_int + 1) * 6 (35mhz) (complex input mode) prog_tic_high, prog_tic_low (write address) prog_tic_high bits 4 to 0: more significant 5 bits of the tic counter division ratio when programmed before a prog_tic_low. prog_tic_low bits 15 to 0: least significant 16 bits of the tic counter division ratio. the prog_tic_high and prog_tic_low register locations operate in conjunction with the front_end_mode bit of the system_setup register to set the period of tic. tic is generated by a 21 bit binary down counter when it reaches zero. it then loads to a preset value stored in its preset register and starts to count down again. if the preset value is p, the count sequence is p, pC1, pC2, ..., 1, 0, p, pC1. hence, the counter divides by p+1 producing an output with a period of (p+1) * clock period. since the tic counter is clocked by the multiCphase clock, the clock period is either 7 * clock period (nominally 40mhz i.e. 25ns) for real_input mode or 6 * clock period (nominally 35mhz i.e. 28.571429ns) for complex_input mode. the value stored in the preset register can be modified in one of two ways: either by toggling the front_end_mode bit of the system_setup register, switching into complex_input mode, or by writing to the prog_tic_high/_low locations. either of these actions will overwrite the previous contents of the preset value. if the tic counter detects an edge on the front_end_mode bit it will load one of two values into the preset register, depending upon its new value. these two presets are as shown in table 13. the value for front_end_mode = low is also that loaded on a master reset. alternatively, the tic counter may be loaded by writing directly to the prog_tic locations. this may be achieved in one of two ways: either the prog_tic_high value can be written, followed by the prog_tic_low value, (at which point the full 21 bits are transferred to the preset register), or just the prog_tic_low value may be written to modify the lower 16 bits of the preset value. it should be noted that in the former case, the top 5 bits programmed as prog_tic_high are stored locally to the tic counter and even if a write to prog_tic_low does not directly follow the write to prog_tic_high, the next prog_tic_low write will still transfer all 21 bits. it is also necessary to ensure that the write to prog_tic_high precedes the write to prog_tic_low, rather than follows it. one further point to note is that the transfer of data to the tic counter data latches occurs under control of the multiCphase clock write cycle and the write to the preset register happens subsequent to the main internal write. to ensure correct operation, a write to system_setup, toggling the front_end_mode bit should not be directly preceded or followed by a write to prog_tic_low. in addition to the 300ns delay normally required between write cycles, a further 100ns delay is required between these two types of writes. a write to system_setup toggling the front_end_mode bit followed directly by a prog_tic_high / prog_tic_low sequence is permissible, since the write to prog_tic_high does not instigate a change of the preset register contents within the tic counter. using the prog_tic write locations the tic period is as follows: tic period = ((prog_tic_high * 65536) + (real_input) prog_tic_low+1)*7/(40mhz) tic period = ((prog_tic_high * 65536) + (complex_input) prog_tic_low+1) * 6/(35mhz) table 12: accum_int period settings front_end_mode interrupt_period preset accum_int period (in system_setup) (in system_setup) low (real_input mode) low 0x0b45 (2885+1)* (7/40mhz) = 505.0500 m s low (real_input mode) high 0x1313 (4883+1)* (7/40mhz) = 854.70000 m s high (complex_input mode) low 0x0b81 (2945+1)* (6/35mhz) = 505.02857 m s high (complex_input mode) high 0x1379 (4985+1)* (6/35mhz) = 854.74286 m s
35 GP2021 table 13: tic period setting front_end_mode preset loaded tic period (in system_setup) low (real_input mode) 0x08b823 (2885+1)* (7/40mhz) = 505.0500 m s high (complex_input mode) 0x08e6a4 (4985+1)* (6/35mhz) = 854.74286 m s reset_control ( write address) bit bit name 15 not used. 14 not used. 13 not used. 12 ch11_rstb 11 ch10_rstb 10 ch9_rstb 9 ch8_rstb 8 ch7_rstb 7 ch6_rstb 6 ch5_rstb 5 ch4_rstb 4 ch3_rstb 3 ch2_rstb 2 ch1_rstb 1 ch0_rstb 0 mrb, active low software master reset mrb: when low (a software reset), the effect is similar to a hardware reset except that the clock generator, the time base generators, measurement data and peripheral functions are not affected and the status bits accum_int, discip, discip_glitch, meas_int, and tic are not reset. mrb should be set to high to allow access to all of the various registers. mrb is set high by a hardware reset. chx_rstb: when set active low, the reset bit inhibits propagation of the clock phases to the chx tracking channel and resets the accumulated data flags, code dco and carrier dco accumulators, the i & d accumulators, and the code phase counter. a chx_rstb does not reset the carrier cycle, code slew or the epoch counters. at the end of the reset, the channel enable resets the code generator to a previously programmed start phase. this is all required for the parallel search algorithm of one satellite signal using many channels in order to start from a known relative code phase on all the channels. all of the control registers in chx can be programmed and read as usual during the reset state. to restart normal operation in several different channels at the same time, the corresponding chx_rstb bits should be set to high during the same write operation. all chx_rstb are set low by a master reset, (both hardware and software), so a write low to bit 0 of this register will force a low onto bits 12 to 1 irrespective of what was on the bus. power consumption can be kept to a minimum by setting chx_rstb low when a channel is not required. status ( write address) bits 15 to 0: not used a write operation to this location, irrespective of the data on the bus, latches the state of all status bits contained in accum_status_a, accum_status_b, and accum_status_c registers. performing a write to status prior to reading the status registers ensures reading of stable status values. the latch takes effect within 300 ns of the trailing edge of the write pulse. the active edge transition of the accum_int signal will also latch the state of the status bits, thus it is not necessary to write to status when the status registers are to be read as a response to the accum_int signal in an interrupt handling routine. the write to status is required only when the status registers are read at times that are not synchronised to the interrupts. these two mechanisms are mutually exclusive and should not be used together C if both are used, a write to status soon after the occurrence of an accum_int signal can result in confused readings. to avoid conflict the interrupt_enable in the system_setup register should be set to low if writes to status are to be used. if the interrupt_enable bit in system_setup register is set to low, the interrupt will not latch the status bits in the status registers, but a status write access will do so. system_setup (write address) bit bit name 15 to 11 not used 10 meas_int_source 9 ops_drive_sel 8 ips_3v_mode 7 interrupt_period 6 front_end_mode 5 interrupt_enable 4 discop_select_100khz 3 discop_select_timemark 2 discop_select_ch0_dump 1 discop 0 carrier_mix_disable meas_int_source: when set high the meas_int output is cleared by a read of meas_status_a, when low by a read of accum_status_b. a master reset forces the meas_int_source bit low. ops_drive_sel: when set high this control bit increases the size of the output driver on accum_int, meas_int, and d(15:0) pins so as to increase the drive of these pins if they are driving a large load. master reset forces ops_drive_sel to low. ips_3v_mode: when set high this control bit sets the input buffers on sign0, mag0, sign1, and mag1 for signals centred on midCsupply, for use with a frontCend running from a 3v supply. when low, sets the thresholds to ttl levels, for 5v operation. master reset forces ips_3v to low. interrupt_period: when low, the approximate interrupt period is set to 505 s and when high it is set to 854 s. for more detail see the description of prog_accum_int. master reset forces interrupt_period bit to low.
36 GP2021 front_end_mode: selects either real_input mode when low or complex_input mode when high. master reset forces front_end_mode to low. interrupt_enable: when set low the effect of the accum_int and meas_int interrupts are disabled (masked) and when set high both are enabled. master reset forces interrupt_enable to low. bits 4 to 1 the signal provided on the discop pin can be selected according to table 14. carrier_mix_disable: when high the carrier mixers are all driven by a fixed +1 level on the carrier dco input port, so that the input data is passed unaltered to the code mixer. master reset forces the carrier_mix_disable bit to low. test_control (write address) bit bit name 15 to 12 not used 11 to 9 path_sel<2:0> 8 en_scanpath 7 not used 6 test_cacodes 5 test_data 4 test_source 3 tm_test 2 fe_test 1 en_dummytics 0 en_dummydump this register is purely to enable various test modes. a master reset will set all bits to low, giving normal operation. en_dummydump: when high, this bit changes the function of the nopc/nintelmot input pin to be a dummydump input, and if in standard interface mode it also forces the microprocessor mode to motorola. a dummydump will operate in the same way as a normal dump (reset all of the code generators and transfer the contents of all integrators into the accumulated data registers). each low to high transition of nopc/nintelmot will cause a dummydump and if nopc/nintelmot is already high when en_dummydump is set, one will also occur immediately. selecting dummy dump mode does not inhibit normal dump events. the nopc/nintelmot pin must be held high for at least 200 ns for each dummydump. en_dummytics: when high this bit changes the function of the discip input pin to a dummytic input. this replaces the tic from the timebase generator so that a tic effect will only occur when there is a low to high transition on discip, to latch new measurement data. the discip pin must be held high for at least 200 ns for each dummytic. fe_test: when high this test control forces the sign input to channel 11 and the mag input to channel 5 both to low. this allows the evaluation of the front_end sign (on channel 5) and mag (on channel 11) duty cycles. the front end to be tested is selected by the sourcesel bits in ch5_satcntl and ch11_satcntl. to get the sign and mag count correctly into the accumulators, both the carrier and code mixers must be made transparent. the carrier mixing may be disabled by either: (1) setting carrier_mix_disable (bit 0 in system_setup) to high to force a +1 on the carrier dco inputs to all channels or, (2) if continued position finding is required from the other channels during the test, by setting ch5_ and ch11_carrier_dco_incr to all 0s, to give a constant level (zero frequency). this level should be set to a known value by putting channels 5 and 11 briefly into the reset state (by using reset_control register bits 6 and 12) during the time their carrier dcos are programmed to zero frequency. this reset forces the phase to all 0s and hence the drives to the prompt inCphase mixer to a fixed +1 and not a randomly selected C2, C1, +1, or +2 that would result from just setting the frequency. the c/a code mixing must be disabled by setting code_off/onb (bits 11 in both ch5_ and ch11_satcntl) to high. however, as the period of the count is set by the dumps from the code generator, the dco clock to the code generator must be set to the required frequency by programming the code dco even though the code output is disabled. a typical value is the frequency for the nominal code chipping rate, so that the sign and mag counts are over a millisecond. the results of monitoring the frontCend of the receiver may be used for fault diagnosis and also for tuning the parameters in the software for optimum satellite tracking with the particular frontCend or sign/mag duty cycle. to find the duty cycle of the sign signal, channel 5 is used. the inCphase accumulator ch5_i_prompt will add +1 for each sign sample at high and will add C1 for each sign sample at low, so if the duty cycle is correct at 50%, the sum will always be close to zero and only differ by the imbalance of sampling at the beginning and end of the integration period. the duty cycle may be calculated as follows: n = total no of samples in integration period. n sign1 = total no of samples for which sign was high. n sign0 = total no of samples for which sign was low. acc5 = total value in the ch5_i_prompt accumulator, as read after a dump. n = n sign1 + n sign0 , acc5 = n sign1 C n sign0 sign duty cycle = r s = n sign1 / n = (n + acc5) / 2n (nominally 0.50) bit signal on discop output 4321 0 0 0 0 0 (reset condition) 00011 0 1 0 x timemark 0 x 1 x ch0 dump 1 x x x 100khz square wave table 10: track_sel bit settings for tracking arm code selection.
37 GP2021 to find the duty cycle of the mag signal, channel 11 is used. the inCphase accumulator ch11_i_prompt will add C3 for each mag sample at high and will add C1 for each mag sample at low. if the duty cycle is correct (30%), the sum will be: C1.6 * (number of samples) plus an allowance for the imbalance of sampling at the beginning and end of the integration period. the duty cycle may be calculated as follows: n = total no of samples in integration period. n mag3 = total no of samples for which mag was high n mag1 = total number of samples for which mag was low acc11 = total value in the ch11_i_prompt accumulator, as read after a dump. n = n mag3 + n mag1 , acc11 = C3 * n mag3 Cn mag1 mag duty cycle, rm = nmag3 / n = C (n + acc11) / 2n (nominally 030). tm_test: when high this bit puts all the tracking modules into a test mode, where it is possible to write to all chx_carrier_cycle_counters and all chx_code_phase_counters. test_source: when high this bit enables a selfCtest generator formed from the ch0 code generator. the data replaces the sign0 and mag0 inputs. it has a chip rate and phase set by the ch0_code_dco and a carrier frequency set by the ch0_carrier_dco. the code is set by writing the appropriate start value into the ch0_satcntl register, and the ch0_slew_counter can be programmed to delay the start of the code generation by a number of half code chips. the three most significant bits of the carrier dco are decoded to give the sign with 50% of highs and the mag with 25% of highs. the sign of the data pattern is set by test_data, exored with the ch0 c/a code. test_data: this bit sets the sign of the modulation of the test data generated when test_source is set. test_cacodes: when high, the inverted prompt codes for all channels, 0 to 11, are available for output on data bus bits 0 to 11 and can be seen in parallel by a read to any ch6 to ch11 read address. en_scanpath: when high the chip is in scan test mode, whereby: discip 1 becomes scan_in discop becomes scan_out multi_fn_io becomes scanclk nopc/nintelmot becomes scansel it should be noted that the discop = scan_out function may be overCridden by the discop_select_100khz function of system_setup. it should also be noted that for correct operation the multi_fn_io pin should be configured as a discrete or scan clock input via the io_config register. path_sel<2:0>: to allow for simple factory testing of the chip, the GP2021 contains six separate scan paths, one for each of the major counters in the chip. only one of these paths may be enabled at any time and the scan path to be used is selected via the path_sel<2:0> bits as follows: path_sel<2:0> scan path selected 000 rtc counters 001 accum_int counter 010 tic counter 011 100khz output counter 100 timemark pulse width counter 101 pll_lock filter counter 11x not used timemark_control (write address) bit bit name 15 to 7 not used 6 to 2 free_run_ratio 1 free_run_timemark 0 arm_timemark the timemark generator operates in one of two ways, either in armed mode, (not related to arm system mode) or in free run mode. in armed mode setting the arm_timemark bit arms the timemark generator which subsequently produces a timemark output pulse coincident with the next rising edge of tic. this then resets the arm_timemark bit ready for a new arming sequence in the future. alternatively, the timemark generator can be used in freeCrun mode, by setting the free_run_timemark bit high. this disables the arm_timemark bit. in free run mode a timemark pulse is produced coincident with the first rising edge of tic after the free_run_timemark bit has been set, and then on an integer number of tics determined by the free_run_ratio bits. in free run mode the timemark period is: timemark period = (free_run_ratio + 1) * tic period (free run mode) all the bits of timemark_control are cleared to low by a master reset. x_dco_incr_high (write address) this register may be used to write the high bits for any carrier or code dco in any channel. a write to x_dco_incr_high must always be followed by a write to the appropriate chx_carrier_dco_incr_low or chx_code_dco_incr_low to define the destination and to complete the action. using x_dco_incr_high rather than chx_carrier C_dco_incr_high gives a quicker way of loading the whole dcos values because the _low write may follow the x_dco_incr high write immediately (without incurring a 300ns wait).
38 GP2021 peripheral functions registers the addresses for the peripheral functions registers are shown in the GP2021 register map. these registers may be either 8 or 16 bits wide. registers which are byte wide are accessed via the top 8 bits of the data bus, d<15:8>. during a byte wide read d<7:0> are held low. each of the registers for the real time clock, dual uart, system and general control functions are described below. real time clock and watchdog the registers in the real time clock are all byte wide. rtc_ls, rtc_2nd, rtc_ms , (read addresses) the clock time is output in these three eight bit read only registers. all three registers are latched when a read is performed of the ls byte register, so this should be read first. in power down mode the clock continues to run but access to these registers is not possible. clock reset (write address) a write to this address resets the clock divider and counter, regardless of the data word written. watchdog reset (write address) a write to this address resets the watchdog timer, regardless of the data word written. duart all the registers within the duart are byte wide. config_a, config_b (write address) these registers allow the uarts to be configured for receive baud rate, parity and loopback. the configuration bit functions are shown in table 15. the missing binary combinations of bit settings should not be used as the results would be indeterminate. note that all bits are set low by a uart a/b or a system reset, thus causing uart a/b to default to a receive baud rate of 300, no parity and no loopback. status_a, status_b (read address) reading from these register addresses will give the current value of the channels status bits. the status bit functions are as shown in table 16. bit set (high) by clearer (low) by reset to 8 rx valid data no rx data low available 9 rx fifo full rx fifo not full low 10 rx fifo read of uart status low overflow register 11 tx tx register empty low transmitting 12 tx fifo full tx fifo not full low 13 parity error read of uart status low occured register low 14 framing error read of uart status low 15 not used (held high) table 16: status bits available when reading the status_a and status_b registers. table 15: configuration of uarts through config_a and config_b registers. bit setting function bit 11 10 9 8 receiver baud rate 0 0 0 0 300 0 0 0 1 600 0 0 1 0 1200 0 0 1 1 2400 0 1 0 0 4800 0 1 0 1 9600 0 1 1 0 19.2k 0 1 1 1 38.4k 1 0 0 0 76.8k bit 13 12 parity 0 0 no parityCbit not set or checked for 1 1 odd parityCparity added so that the toatl number of '1's in the word is even 1 0 even parityCparity added so that the total number of '1's in the word is even bit 14 loopback 0 no loopbackCnormal operation 1 loopbackCthe tx output drives the rx input and tx pin is held high bit 15 test mode 0 test mode bit in ch a only used for chip testing only. this bit must be set low for normal operation 1 test mode
39 GP2021 bit 11 10 9 8 receiver baud rate 0 0 0 0 300 0 0 0 1 600 0 0 1 0 1200 0 0 1 1 2400 0 1 0 0 4800 0 1 0 1 9600 0 1 1 0 19.2k 0 1 1 1 38.4k 1 0 0 0 76.8k tx_rate_a, tx_rate_b (write address) these are write registers for uarts a and b which allow the transmit baud rates to be set as shown in table 17. the missing binary combinations of bit settings should not be used as the results would be indeterminate. note 1 . the conditions after a reset are:C rom wait states= 3, eeprom and spare wait states = 5+1. system_config (write / read address) this is a read/write register (8 bits wide), which allows the watchdog function to be enabled and disabled via bit 9. note that following a system reset this bit is set low, thus enabling the watchdog. reset_a, reset_b (write address) writing to this register will reset the uart a/b, regardless of the data word written. tx_data_a, tx_data_b, rx_data_a, rx_data_b (write / read address) these are read/write addresses to uarts a and b, which allow bytes to be written to the tx fifos or received from the rx fifos. table 17: transmit baud rate settings in the tx_rate_a and tx_rate_b registers. bits 12 to 15 are not used and may be set high or low. note that bits 8 to 11 are set low by a uart a/b or system reset, thus causing the transmitter to default to a baud rate of 300. system control wait_state (write / read address) this is a read/write register (8 bits wide), which allows the rom (read/write) wait state and eeprom and spare (read) wait states to be configured via bits 8 to 11. eeprom and spare read accesses consist of 2C5 wait states whilst mclk is high, increasing the read access time, followed by 1 trailing wait state whilst mclk is low to allow for a greater bus release time. the chip revision number appears on bits 12 to 15 when read. bit 9 8 rom (read/write) wait states 00 1 01 2 10 3 1 1 1 unused (3) bit 10 11 eeprom ans spare (read) wait states 0 0 2+1 0 1 3+1 1 0 4+1 1 1 5+1 1 table 18: wait_state register settings. bits 15 to 10 and 8 are not used and could be set high or low. the chip revision number appears on bits 12 to 15 when read. system_error_status this is an 8 bit wide read only register, and allows the source of a system reset to be determined via bits 11 to 8. it is reset to all low after being read. the chip revision number appears on bits 12 to 15 when read. bit 8 : set during a system reset , when the source of the reset is a pll_lock failure. bit 9 : set during a system reset, when the source of the reset is the watchdog. bit 10 : set during a system reset, when the source of the reset is a power_good failure. bit 11 : set during a system reset, when the source of the reset is the external nreset_ip. note that this reset source is only available in standard interface mode. chip_revision (read addresses) the chip_revision register is a read only register which exists as the high 4 data bits of the wait state, system configuration and system error status registers. a read of any of these three registers will output the chip_revision information on bits 15 to 12. this register is intended to allow software discrimination of revisions of the GP2021, both pre production revisions and possible customer specific variants. the initial production version of the GP2021 will have a chip_revision of 0011. bit 9 watchdog function 0 enabled 1 disabled table 19: enableing the watchdog function through the system_config register
40 GP2021 data_retent (write / read address) this is a byte wide read/write register which can be used to store a predetermined value, which can be interrogated in order to determine whether a total power loss (below the data retention level ) has occurred. general control io_config (write / read address) the io_config register is a full 16 bit wide read/write register containing two separate elements: a 16 bit wide read location which allows the controlling microprocessor to view the input level on all the discrete and multi function inputs, and a 16 bit wide write location for configuration of the discreteand multi function i/o pins. io_config read: a read of the io_config address will latch the logic level of a number of input pins and output these levels to the microprocessor via the 16 bit data bus. this allows the microprocessor to read the input levels on all the discrete and multi function inputs from a single location. the bit allocations are as follows: bit input pin 15 rxb 14 rxa 13 discop 12 discip 11 mag1 10 sign1 9 mag0 8 sign0 7 multi_fn_io 6 nbram 5 discio 4 narmsys 3 nbw/wrprog 2 nmreq 1 nopc/nintelmot 0 nrw it should be noted that the usefulness of a number of these inputs as discrete inputs for system control is dependant upon the interface mode of the GP2021. for instance it is possible to use the nopc/nintelmot pin as a discrete input in arm system mode if the debug function is disabled, whereas this pin could not be used as a discrete input in standard interface mode. similarly, nmreq could be used as a discrete input in standard interface mode but not in arm system mode. io_config write: the io_config write location allows the configuration of the multi purpose i/o pins discio and multi_fn_io. the register bit assignments are as follows: bit bit name 15 to 13 not used 12 multi_fn_io_select_timemark 11 multi_fn_io_select_100khz 10 multi_fn_io_level 9 to 8 multi_fn_io_config 7 to 4 not used 3 discio_select_timemark 2 discio_select_100khz 1 discio_level 0 discio_config discio_config: when set high this bit configures the discio pin as a discrete output, when low the discio pin is configured as a discrete input. a master reset sets the discio_config bit low. discio_select timemark, discio_select_100khz, discio_level: when configured as an output, the discio pin can be setup to give a signal as determined by table 20. at power on reset, the discio output value = 0 setting is chosen. the 100khz square wave is derived from the master clock and is useful for measuring its drift. multi_fn_io_select timemark, multi_fn_io_select_100khz, multi_fn_io_level: when configured as an output, the multi_fn_io pin can be setup to give a signal as shown in table 21 bit discio output value 32 1 00 0 0 00 1 1 0 1 x 100khz square wave 0 x x timemark table 20: discio output selection. bit discio output value 12 11 10 00 0 0 00 1 1 0 1 x 100khz square wave 0 x x timemark table 21: multi_fn_io output selection.
41 GP2021 multi_fn_io_config: these 2 bits configure the function of the multi_fn_io input as follows: bits <9:8> multi_fn_io function 00 digital system test enable input 01 trigger input 10 discrete input (see description) / scan clocks input 11 discrete output master reset sets bits 9 and 8 to low. multi_fn_io as digital system test enable input: allows testing of the digital section of the system board. in this mode, when multi_fn_io is high, the rxa pin replaces the differential master clock inputs and the rxb pin acts as an rtc reset input. the pll_lock filter is also disabled. for more information see the digital system test mode description. multi_fn_io as trigger input: the debug function is enabled if in arm system mode and the multi_fn_io pin acts as the trigger input to the debug block. for more information see the debug block description. multi_fn_io as discrete input / scan clocks: in this mode the pin has 2 functions: as a discrete input and as the scan clocks input for chip scan path testing. it should be noted that the multi_fn_io pin should only be used as a discrete input with caution. since the master reset default is for multi_fn_io to act as the digital system test enable input it must be guaranteed that anything driving this pin as a discrete input must have a low output until the io_config register can be written to and discrete input mode enabled. test_config (write address) the test_config register is a 3 bit wide writeConly register which complements the test_control register of the correlator but contains chip test control bits for peripheral functions. the register bit assignments are as follows: bit bit name 10 rtc_test_count 9 rtc_reset_enable 8 wdog_reset_disable rtc_test_count : when set high this bit splits up the 24 bit counter of the rtc which counts seconds into a number of 4 bit counters to allow easier chip testing. the 24 bit rtc counter is not scan path testable. a master reset sets the rtc_test_count bit low. rtc_reset_enable: when set high this bit enables the rxb pin to act as an rtc reset input, which then resets the rtc and watchdog counters whenever rxb is taken high. this function is intended for factory testing of the GP2021. a master reset forces the rtc_reset_enable bit low. wdog_reset_disable: when set high this bit inhibits the production of system resets from the watchdog counter, without disabling the watchdog counter itself. this function is intended for scan path testing of the watchdog and rtc counters. a master reset forces the wdog_reset_disable bit low. data_bus_test (write / read address) this is a 16 bit read/write register, whose function is to allow a simple test of the 16 bit wide data bus to be performed, by writing a 16 bit number and by checking that the same value can be read back. absolute maximum ratings these are not the operating conditions, but are the absolute limits which if exceeded, even momentarily, may cause permanent damage. to ensure sustained correct operation the device should be used within the limits given under electrical characteristics. it is essential for bothv dd and v ss to be present before input signals are applied. supply voltage (v dd ) from ground (v ss ): C0.3 to+6.0v input voltage (any input pin): v ss C0.3v to v dd + 0.3v output voltage (any output pin): v ss C0.3v to v dd +0.3v storage temperature: C55 c to +150 c electrostatic discharge protection (esd) the device is able to withstand an electrostatic discharge level of 2kv from 100pf through 1500 between any two pins in either polarity (mil. std. 883 human body model). crystal specification frequency: 32.768khz temperature range: C40 ? c to +85 ? c series resistance: 50k w w typ, 100 w max load capacitance: 10pf typical
42 GP2021 electrical characteristics t amb = C40 c to 85 c, v dd = 5v 10%. the input thresholds and output voltage limits for the logic signal pins are tested and guaranteed by production test. all other parameters are guaranteed by characterisation and design. they apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. value characteristics symbol min typ max units conditions supply current i dd 22 ma 0 channels enabled. 27 ma 4 channels enabled. 32 ma 8 channels enabled. 38 ma 12 channels enabled. 20 150 m a power down mode 2.2v C 3.3v (note 3) 50 500 m a power down mode 5.0v (note 3) battery backup voltage v batt 2.2 v power down mode all ttl inputs, with and without pullCup or pullCdown resistors: type ttl high level input voltage 2.0 v low level input voltage 0.8 v schmitt trigger inputs type st1 positiveCgoing threshold vi + 1.9 2.3 v v dd = 3v negativeCgoing threshold vi C 0.8 1.2 v v dd = 3v hysteresis vh 0.35 0.7 v v dd = 3v schmitt trigger inputs type st2 positiveCgoing threshold vi + 1.72 2.32 v negativeCgoing threshold vi C 0.72 1.10 v hysteresis vh 0.3 0.62 v master clocks : type diff note 2 input voltage high 0.8v dd v d.c. coupled input voltage low 0.2v dd v d.c. coupled or d.c. coupled differential sinewave (pkCpk) 130 mv mid point at nominal 4.3v or peak to peak single sinewave 600 mv ac coupled crystal oscillator type xtli, xtlo frequency range f osc 32 1000 khz amplifier transconductance gm 220 550 2500 m a/v output impedance z0 20 56 100 kw
43 GP2021 electrical characteristics(cont.) t amb = C40 c to 85 c, v dd = 5v 10%. the input thresholds and output voltage limits for the logic signal pins are tested and guaranteed by production test. all other parameters are guaranteed by characterisation and design. they apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. value characteristics symbol min typ max units conditions power level 6 outputs: types op6 and opt6 output voltage high v oh 0.8v dd vi oh = C12ma output voltage low v ol 0.4 v i ol = 12ma output short ios 270 ma v dd = max vo = v dd circuit current 150 ma v dd = max vo = 0v triCstate output leakage current ioz <10 m a voh = gnd or v dd output capacitance cout 5 pf power level 3 outputs : types op3 and opt3 output voltage high v oh 0.8v dd vi oh = C6ma output voltage low v ol 0.4 v i ol = 6ma output short ios 135 ma v dd = max vo = v dd circuit current 75 ma v dd = max vo = 0v triCstate output leakage current ioz <10 m a voh = gnd or v dd output capacitance cout 5 pf power level 2 outputs: types op2 and opt2 output voltage high v oh 0.8v dd vi oh = C4ma output voltage low v ol 0.4 v i ol = 4ma output short ios 90 ma v dd = max vo = v dd circuit current 50 ma v dd = max vo =0v triCstate output leakage current ioz <10 m a voh = gnd or v dd output capacitance cout 5 pf power level 1 outputs: types op1 and opt1 output voltage high v oh 0.8v dd v i oh = C2ma output voltage low v ol 0.4 v i ol = 2ma output short ios 45 ma v dd = max vo = v dd circuit current 25 ma v dd = mx vo = v dd triCstate output leakage current ioz <10 m a voh = gnd or v dd output capacitance cout 5 pf note 1: any unused inputs must be tied high or low. note 2: the input pair clk_t, clk_i may be driven by cmos logic levels (d.c. coupled) or a.c. coupled or by a low amplitude differentia l sinewave (d.c. coupled e.g. gp2010). if a single logic level is to be used this should drive clk_t with the clk_i pin biased to mid supply. if a single sinewave clock is to be used this should drive clk_t through a capacitor, with both of the clk_t/clk_i pins biased to approximately two thirds supply. see fig. 24 for a suggested circuit. note 3 : these values apply when the 32khz oscillator circuit is not running. note 4: the operation of the feature whereby input levels and output drive strengths can be modified is not guaranteed by the existing factory testing procedure.
44 GP2021 pin types the following table defines the type of each pin and additional notes relating to them. pin no pin name pin type input type pull up/dn o/p type triCstate notes 1 multi_fn_io i/o st2 75k dn opt3 yes 1 2 power_good ip st2 none C C 3 nreset_op op C C op3 no 4 narmsysip st2 none C C 5 xin ip xtli none C C xtal in 6 xout op C C xtlo no xtal out 7 txa op C C op6 no 8 txb op C C op6 no 9 rxa ip st2 none C C 10 rxb ip st2 none C C 11 nrom / nc op C C opt6 yes 9 12 neeprom / nc op C C opt6 yes 8 13 nspare_cs / nc op C C opt6 yes 9 14 v dd v dd C C C C 15 v ss v ss C C C C 16 nram / nc op C C op6 no 10 17 nw0 / ncop C C op6 no 11 18 nw1 / ncop C C op6 no 10 19 nw2 / ncop C C op6 no 10 20 nw3 / ncop C C op6 no 10 21 nrd / ncop C op6 no 11 22 arm_ale / nc op C C op6 no 8 23 dbe / nc op C C op6 no 8 24 accum_int op C C opt1/opt2 yes 2, 6 25 meas_intop C C opt1/opt2 yes 2, 7 26 nbw / wrprog ip ttl none C C 27 nmreq / discip2 ip ttl none C C 28 nopc / nintelmot ip ttl none C C 29 nrw / discip3 ip ttl none C C 30 mclk / nc op C C op6 no 8 31 abort / micro_clk op C C op3 no 32 discio i/o st2 none opt3 yes 33 a22 / read ip ttl/st2 none C C 3 34 v dd v dd C C C C 35 v ss v ss C C C C 36 a21 / ncs ip ttl/st2 none C C 3 37 a20 / wren ip ttl/st2 none C C 3 38 a9 ip ttl none C C 39 a8 ip ttl none C C 40 a7 ip ttl none C C 41 a6 ip ttl none C C 42 a5 ip ttl none C C 43 a4 ip ttl none C C 44 a3 ip ttl none C C
45 GP2021 pin no pin name pin type input type pull up/dn o/p type triCstate notes 45 a2 ip ttl none C C 46 a1 / ale_ip i p ttl/st2 none C C 3 47 a0 / nreset_ip ip ttl/st2 none C C 3 48 d0 i/o ttl none opt3/opt6 yes 4, 12 49 d1 i/o ttl none opt3/opt6 yes 4, 12 50 d2 i/o ttl none opt3/opt6 yes 4, 12 51 d3 i/o ttl none opt3/opt6 yes 4, 12 52 d4 i/o ttl none opt3/opt6 yes 4, 12 53 d5 i/o ttl none opt3/opt6 y es 4, 12 54 d6 i/o ttl none opt3/opt6 yes 4, 12 55 v dd v dd C C C C 56 v ss v ss C C C C 57 d7 i/o ttl none opt3/opt6 yes 4, 12 58 d8 i/o ttl none opt3/opt6 yes 4, 12 59 d9 i/o ttl none opt3/opt6 yes 4, 12 60 d10 i/o ttl none opt3/opt6 yes 4, 12 61 d11 i/o ttl none opt3/opt6 yes 4, 12 62 d12 i/o ttl none opt3/opt6 yes 4, 12 63 d13 i/o ttl none opt3/opt6 yes 4, 12 64 d14 i/o ttl none opt3/opt6 yes 4, 12 65 d15 i/o ttl none opt3/opt6 yes 4, 12 66 pll_lock ip st2 none C C 67 v dd v dd C C C C 68 discop op C C opt3 yes 69 v ss v ss C C C C 70 clk_t ip diff none C C 71 clk_i ip diff none C C 72 v ss v ss C C C C 73 sampclk op C C op2 no 13 74 v dd v dd C C C C 75 nbram / discip4 ip st2 none C C 76 sign0 ip st2/st1 none C C 5, 13 77 mag0 ip st2/st1 none C C 5, 13 78 sign1 ip st2/st1 none C C 5, 13 79 mag1 ip st2/st1 none C C 5, 13 80 discip1 ip st2 none C C
46 GP2021 notes : 1. although multi_fn_io is capable of being used as a discrete input, this is not advised since if this pin is driven high at power up, digital test mode will be selected and correct operation will not ensue. 2. output has power level 1 when ops_drive_sel is low in the system_setup register. output has power level 2 when ops_drive_sel is high in the system_setup register. 3. input has ttl thresholds in arm system mode, but has schmitt trigger (type st2) thresholds in standard interface mode. 4. output has power level 3 when ops_drive_sel is low in the system_setup register. output has power level 6 when ops_drive_sel is high in the system_setup register. 5. input has schmitt trigger type st2 thresholds when ips_3v_mode is low in the system_setup register. when high they have st1 thresholds. 6. usually connected to nfiq of the arm60 processor. 7. usually connected to nirq of the arm60 processor. 8. characterisation data for this pin is with c l = 10pf. 9. characterisation data for this pin is with c l = 20pf. 10. characterisation data for this pin is with c l = 30pf 11. characterisation data for this pin is with c l = 50pf. 12. characterisation data for this pin is with c l = 55pf. 13. setup and hold times for the gps data applied on pins sign0, mag0, sign1 and mag1 are with respect to the rising edge of sampclk. setup time = 15ns, hold time = C1ns (i.e. data should not change during the period between 15ns and1ns before the rising edge of sampclk; where sampclk is assumed to be un loaded. the sampclk signal will tend to be further delayed by about 0.1ns / pf of load capacitance). v dd v dd 100k 100k clk_t clk_i or 100k 0.1 t o 1nf 600mv sine wave 180k 0.1 t o 1nf clk_t clk_i or gp2010 differential output opclk+ clk_t opclk clk_i v ss v ss single ended cmos differential single 600mv sinew ave 100k fig 24 : clock interconnect options
47 GP2021 mclk dbe a<22:20> arm internal arm_ale d<15:0> mchall mchdbh mcldbl valid valid valid address mclalh a<9:0> fig. 25 :GP2021 - arm60 interfsce description symbol min max units mclk low to ale high t mclaih C0.5 0 ns mclk high to ale low t mchail 0 0.5 ns mclk low to dbe low t mcldbl 0.5 1.5 ns mclk high to dbe high t mchdbh 0.5 1.5 ns mclk dbe d<15:0> a<22:20> nram nw arm data advnral mclnwh dbhnwh nralnwh nwl fig. 26 :arm mode ram write description symbol min max units nram low to nw0C3 high t nralnwh 32 46 ns mclk low to nw0C3 high t mclnwh 0.5 3 ns dbe high to nw0C3 high t dbhnwh 25 27 ns nw0C3 low t nwl 22 24.5 ns address valid to nram low t advnral 29ns
48 GP2021 mclk dbe d<15:0> a<22:20> nram nrd ram data advnral nralmcl nrdlmcl nrdhdbh mclnrdh ram read cycle fig. 27 : arm mode ram read description symbol min max units nram low to mclk low t nralmcl 29 45 ns nrd low to mclk low t nrdlmc l 16.5 23 ns nrd high to dbe high t nrdhdbh 15.5 22.5 ns mclk low to nrd high t mclnrdh 2.5 11.5 ns address valid to nram low t advnral 28 ns
49 GP2021 mclk dbe d<15:0> a<22:20> nrom nw arm data dbhnwh nwhmcl advnrol nrolnwl nrol nwl nwh a<9:0> nwhnroh fig. 27 : arm mode ram read description symbol min max units notes nrom low t nrol 100 ns 1 nrom low to nw0C3 low t nrolnwl 11 21.5 ns dbe high to nw0C3 high t dbhnwh 52 57 ns 1 nw0C3 low t nwl 50 51 ns 1 nw0C3 high to mclk low t nwhmcl 16 23 ns nw0C3 high to nrom high t nwhnroh 27.5 39 ns nw0C3 high t nwh 47 49 ns address valid to nrom low t advnrol 2 7.5 ns note: 1. +50ns / extra wait state rom data d<15:0> nrd mclk nrom a<22:20> dbe nrolmcl nrdlmcl advnrol nrdhdbh mclnrdh a<9:0> fig. 27 : arm mode rom read description symbol min max units notes nrom low to mclk low t nrolmcl 48 74.5 ns 1 nrd low to mclk low t nrdlmcl 48 50 ns 1 nrd high to dbe high t nrdhdbh 33 45 ns mclk low to nrd high t mclnrdh 2.5 10 ns address valid to nrom low t advnrol 2.5 9 ns note: 1. +50ns / extra wait state
50 GP2021 mclk dbe d<15:0> a<22:20> neeprom/nspare_cs nw arm data dbhnwh nwhdbl advneel neelnwl neel nwl nwh a<9:0> eeprom/sp are data d<15:0> nrd mclk neeprom/nspare_cs a<22:20> dbe neelmcl nrdlmcl advneel nrdhdbh mclnrdh a<9:0> fig. 27 : arm mode ram read description symbol min max units neeprom low t neel 348 ns neeprom low to nw0C3 t neelnwl 11 ns nw0C3 low t nwl 1 50 ns nw0C3 high t nwh 200 ns dbe high to nw0C3 high t dbhnwh 150 ns nw0C3 high to dbe low t nwhdbl 168 ns address valid to neeprom low t advneel 2.5 9 ns fig. 27 : arm mode ram read description symbol min max units notes neeprom low to mclk low t neelmc l 124.5 ns 1 nrd low to mclk low t nrdlmcl 117 ns 1 nrd high to dbe high t nrdhdbh 65 ns mclk low to nrd high t mclnrdh 2.5 10 ns address valid to neeprom low t advneel 2.5 9 ns note: 1. +50ns / extra wait state
51 GP2021 eeprom/sp are data d<15:0> nrd mclk neeprom/nspare_cs a<22:20> dbe neelmcl nrdlmcl advneel nrdhdbh mclnrdh a<9:0> fig. 32 : intel 486 mode write (narmsys = 1, nintelmot = 0, wrprog = !) timing parameter description symbol min max units notes ale_ip high to wren and ncs low setup time t alhwcl 5ns ale_ip high to ale_ip low pulse width t alhall 13 ns ale_ip low to wren or ncs high pulse width t allwch 10 ns 1 wren and ncs low to wren or ncs high pulse width t wclwch 10 ns wren or ncs high to ale_ip high holdCoff time t wchalh 5ns address valid to ale_ip low setup time t advall 9ns ale_ip low to address invalid hold time t alladi 8ns data valid to wren or ncs high setup time t davwch 7ns wren or ncs high to data invalid hold time t wchdai 5ns note: 1 write inhibited until ale_ip falling edge.
52 GP2021 timing parameter description symbol min max units notes ale_ip high to wren and ncs low setup time t alhwcl 5ns ale_ip high to ale_ip low pulse width t alhall 13 ns ale_ip low to wren or ncs high pulse width t allwch 10 ns 1 wren and ncs low to wren or ncs high pulse width t wclwch 10 ns wren or ncs high to ale_ip high holdCoff time t wchalh 5ns address valid to ale_ip low setup time t advall 9ns ale_ip low to address invalid hold time t alladi 8ns data valid to wren or ncs high setup time t davwch 7ns wren or ncs high to data invalid hold time t wchdai 5ns note: 1 write inhibited until ale_ip falling edge. 2 the ale_ip low to data output valid delay assumes ale_ip is overlapping the read and ncs low time. if not, the t allda v parameter applies from the point at which both read and ncs are low. 3. the data out propagation delay is for a data bus load of 50pf. wren ncs read ale_ip a<9:2> alhall advall alladi address valid alldav rchdaz rchalh d<15:0> (high) alhrcl fig. 33 : intel 486 mode read (narmsys = 1, nintelmot = 0, wrprog = 1)
53 GP2021 timing parameter description symbol min max units notes wren and ncs low to wren or ncs high pulse width t wclwch 10 ns address valid to wren and ncs low setup time t advwcl 9ns wren or ncs high to address invalid hold time t wchadi 10 ns data valid to wren or ncs high setup time t davwch 7ns wren or ncs high to data invalid hold time t wchdai 5ns wren ncs ale_ip a<9:2> d<15:0> data valid advwcl wchadi davwch wchdai address valid wclwch (high) read (high) fig. 34 : intel 186 mode write with ale_ip tied high (narmsys = 1, nintelmot = 0, wrprog = 0)
54 GP2021 timing parameter description symbol min max units notes address valid to read and ncs low setup time t advrcl 9ns read or ncs high to address invalid hold time t rchadi 10 ns read and ncs low to data valid propagation delay t rcldav 44 ns 1 read or ncs high to data high impedance t rchdaz 423ns notes: 1 the data out propagation delay is for a data bus load of 50pf. read ncs ale_ip a<9:2> d<15:0> adlrcl address valid data valid rcldav rchdaz (high) d<15:0> wren (high) rchadi fig. 35 : intel 186 mode read with ale_ip tied high (narmsys + 1, nintelmot = 0, wrprog = 0)
55 GP2021 timing parameter description symbol min max units notes ale_ip high to wren and ncs low setup time t alhwcl 14 ns ale_ip high to ale_ip low pulse width t alhall 10 ns wren and ncs low to wren or ncs high pulse width t wclwch 10 ns wren or ncs high to ale_ip high hold off time t wchalh 5ns address valid to wren and ncs low setup time t advwcl 10 ns address valid to ale_ip low setup time t advall 8 ns ale_ip low to address invalid hold time t alladi 8ns data valid to wren or ncs high setup time t davwch 7ns wren or ncs high to data invalid hold time t wchdai 5ns alhwcl wren ncs ale_ip a<9:2> d<15:0> data valid advwcl alladi davwch wchdai address valid read wclwch alhall wchalh advall (high) fig. 36 : intel 186 mode writewith ale_ip being pulsed (narmsys = 1, nintelmot = 0, wrprog = 0)
56 GP2021 timing parameter description symbol min max units notes ale_ip high to read and ncs low setup time t alhrcl 14 ns ale_ip high to ale_ip low pulse width t alhall 10 ns read or ncs high to ale_ip high hold off time t rchalh 5ns address valid to read and ncs low setup time t advrcl 10 ns address valid to ale_ip low setup time t advall 8ns ale_ip low to address invalid hold time t alladi 8ns read and ncs low to data valid propagation delay t rcldav 44 ns 1 read or ncs high to data high impedance t r chdaz 423 ns notes: 1 the data out propagation delay is for a data bus load of 50pf. read ale__ip a<9:2> d<15:0> rchalh alhall advall alladi rcldav rchdaz address valid ncs alhrcl advrcl wren (high) fig. 37 : intel 186 mode read ale_ip being pulsed (narmsys = 1, nintelmot = 0, wrprog = 0)
57 GP2021 timing parameter description symbol min max units notes wren or ncs inactive to wren and ncs active t wciwca 23 ns 1 wren and ncs active to wren or ncs inactive t wcawci 10 ns 1 ale_ip high to ale_ip low pulse width t alhall 13 ns wren or ncs inactive to ale_ip low hold off time t wciall 23 ns 1 address valid to ale_ip low setup time t advall 9ns ale_ip low to address invalid hold time t alladi 8ns read valid to wren and ncs active setup time t rdvwca 7 ns 1, 2 wren and ncs active to read invalid hold time t wcardi 5 ns 1, 2 data valid to wren or ncs inactive setup time t davwci 7ns1 wren or ncs inactive to data invalid hold time t wcidai 5ns1 notes: 1 wren is active high, ncs is active low. 2 read is transparently latched by wren and ncs being active. 3 there is no parameter specified for wren or ncs inactive to ale_ip high, since the internal ale signal is disabled until after the end of the internal read or write strobe; hence the need for the t wciall parameter. wren ncs read ale_ip a<9:2> d<15:0> data valid wciwca rdvwca wcardi wciall alhall advall alladi davwci wcidai wcawci address valid fig. 38 : motorola mode write, ale_ip non-overlapping wren and ncs (narmsys = 1, nintelmot = 1, wrprog = x)
58 GP2021 timing parameter description symbol min max units notes wren or ncs inactive to wren and ncs active t wciwca 23 ns 1 ale_ip high to ale_ip low pulse width t alhall 13 ns wren or ncs inactive to ale_ip low hold off time t wciall 23 ns 1 address valid to ale_ip low setup time t advall 9ns ale_ip low to address invalid hold time t alladi 8ns read valid to wren and ncs active setup time t rdvwca 7 ns 1, 2 wren and ncs active to read invalid hold time t wcardi 5 ns 1, 2 wren or ncs active to data valid t wcadav 44 ns 1 wren or ncs inactive to data high impedance t wcidaz 423 ns1 notes: 1 wren is active high, ncs is active low. 2 read is transparently latched by wren and ncs being active. 3 there is no parameter specified for wren or ncs inactive to ale_ip high, since the internal ale signal is disabled until after the end of the internal read or write strobe; hence the need for the t wciall parameter. wren ncs read ale_ip a<9:2> d<15:0> data valid wciwca rdvwca rdiwca wciall alhall advall alladi wcadav wcidaz address valid fig. 39 : motorola mode read, ale_ip non-overlapping wren and ncs (narmsys = 1, nintelmot = 1, wrprog = x)
59 GP2021 timing parameter description symbol min max units notes wren or ncs inactive to wren and ncs active t wciwca 23 ns 1 wren and ncs active to wren or ncs inactive t wcawci 10 ns 1 ale_ip high to wren and ncs active pulse width t alhwca 13 ns 1 wren and ncs active to ale_ip low hold time t wcaall 6 ns 1, 2 address valid to wren and ncs active setup time t advwca 9ns1 wren and ncs active to address invalid hold time t wcaadi 11 ns 1 read valid to wren and ncs active setup time t dvwca 7 ns 1, 3 wren and ncs active to read invalid hold time t wcardi 5 ns 1, 3 data valid to wren or ncs inactive setup time t davwci 7ns1 wren or ncs inactive to data invalid hold time t wcidai 5ns1 notes: 1 wren is active high, ncs is active low. 2 if ale_ip does not overlap wren and ncs active by wcaall then the timings for ale_ip both overlapping and nonCoverlapping wren and ncs active must be met. 3 read is transparently latched by wren and ncs being active. 4 there is no parameter specified for wren or ncs inactive to ale_ip high, since the internal ale signal is disabled until after the end of the internal read or write strobe; hence the need for the wciall parameter. wren ncs read ale_ip a<9:2> d<15:0> data valid wciwca rdvwca wcardi alhwca advwca wcaadi davwci wcidai address valid wcaall wcawci fig. 40 : motorola mode read, ale_ip overlapping wren and ncs (narmsys = 1, nintelmot = 1, wrprog = x)
60 GP2021 timing parameter description symbol min max units notes wren or ncs inactive to wren and ncs active t wciwca 23 ns 1 wren and ncs active to wren or ncs inactive t wcawci 10 ns 1 ale_ip high to wren and ncs active pulse width t alhwca 13 ns 1 wren and ncs active to ale_ip low hold time t wcaall 6 ns 1, 2 address valid to wren and ncs active setup time t advwca 9ns1 wren and ncs active to address invalid hold time t wcaadi 11 ns 1 read valid to wren and ncs active setup time t rdvwca 7 ns 1, 3 wren and ncs active to read invalid hold time t wcardi 5 ns 1, 3 data valid to wren or ncs inactive setup time t davwci 7ns1 wren or ncs inactive to data invalid hold time t wcidai 5ns1 notes: 1 wren is active high, ncs is active low. 2 if ale_ip does not overlap wren and ncs active by wcaall then the timings for ale_ip both overlapping and nonCoverlapping wren and ncs active must be met. 3 read is transparently latched by wren and ncs being active. 4 there is no parameter specified for wren or ncs inactive to ale_ip high, since the internal ale signal is disabled until after the end of the internal read or write strobe; hence the need for the wciall parameter. wren ncs read ale_ip a<9:2> d<15:0> data valid wciwca rdvwca rdiwca alhwca advwca wcaadi wcadav wcidaz address valid wcaall fig. 41 : motorola mode read, ale_ip overlapping wren and ncs (narmsys = 1, nintelmot = 1, wrprog = x)

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